vhdl

vhdl

Count two up/down pulse streams with one counter? [closed]

How do i get a 100kbps clock for an I2C on Quartus Prime?

Handling very large vector in VHDL

Strange VHDL behavior on hardware unlike simulation

I2C slave NACK with multiple slaves

VHDL - access to 2D array of std_logic_vectors gives unexpected bus conflict

modelsim says: near ")": (vcom-1576) expecting IDENTIFIER. but fixing it gives more errors

Instantiate VHDL entity with 2D array from SystemVerilog

vunit, what are reset conditions between test case

Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus

VHDL Frequency Meter that reads NCO

String in VHDL Waveform

why my shift register show the result in one clock instead of 4?

VHDL Counter mod 60

How to control routing in Altera Cyclone V FPGA

how to change the value of one signal in two different processes? in vhdl

What is this VHDL 10309 error code all about?

Common 17-165 Too many positional options when parsing

How to check the state machine case in testbench

Beginner with Spartan 6, syntax issue

how to make a fully generic MUX in VHDL 93

Can signal in std_logic have other value than 0 and 1?

VHDL - Using output of one entitiy as input of another

Mysterious bit mismatch for VHDL

Unable to output data entered into a register

FSM enters impossible state

Partially constrained vector and arrays in VHDL

8 bit serial to parallel shifter in vhdl

how can i make a testbech of the basic VHDL code?

Is there a way to rename std_logic_vector to a shorter name like 'v'?

VHDL - Adding/Removing Pipeline Register with Generics

What's the difference between `transaction and `transaction`event in VHDL

Why in the Design Timing Summery (synthesis) in Vivado i get WNS = inf?

Internal signal type error in Test Bench VHDL

Verilog int unsigned VHDL equivalent

vhdl ERRROR: Attribute "range" requires a constrained array prefix

Generic function in VHDL to extract an arbitrary byte from a std_logic_vector of any length?

vhdl clock input to output as a finite state machine

In VHDL, how to initialize MSB's of std_logic_vector to zeros and LSB's to a std_logic_vector literal such as "10101111001"

load VHDL sram from a file

VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter

Unable to output data from ram memory address

How to use only one DUT for different test cases in a VHDL testbench and how to detect SPI master's mode on the slave side?

In VHDL, check if an access is null from an if statement?

Parse error: unexpected WHEN, expecting SEMICOLON

My VDHL code runs incorrectly - square root in vhdl

How does vhdl's concatenation operator work and how is it different from verilog

repetitive input/output entity declaration vhdl

Counter 0-30 But Clock connected - VHDL code

emulating systemverilog interfaces in VHDL using record types?

Would like someone to double check code for 8bit up counter with enable

Interacting like a Mealy machine in sequential VHDL

Vivado stops simulation on feedback circuit

What does this C value mean?

NEXSYS A7 Board - I2S2 PMOD

Can you import a vhdl package in a systemverilog file?

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks

space is required between number and unit name

Changing triggering edge depending on clock polarity signal

Use component and process together vhdl

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