load VHDL sram from a file - vhdl

Question

I was curious why the following code doesn't work to load an sram memory array in VHDL? What am I missing?
here's my input file: ram_image.hex
be
ef
ca
fe
34
23
Here's the code where i attempt to load my_ram using the impure function load_sram_hex.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity sram is
end entity;
architecture beh of sram is
constant sram_dw :integer := 8;
constant sram_aw :integer := 4;
constant sram_depth :integer := 2**sram_aw - 1;
type sram_t is array (0 to sram_depth-1) of std_logic_vector(sram_dw downto 0);
impure function load_sram_hex(filename : in string) return sram_t is
file f :text is in filename;
variable b :line;
variable mem :sram_t;
variable good :boolean;
variable m :line;
begin
for i in sram_t'range loop
readline(f, b);
hread(b, mem(i), good);
write(m, string'("HERE=> ") );
hwrite(m, mem(i));
writeline(output, m);
if (not good) then
exit;
end if;
end loop;
return mem;
end function;
signal my_ram : sram_t := load_sram_hex("ram_image.hex");
begin
process
variable m :line;
begin
wait for 10 ns;
for i in sram_t'range loop
write(m, string'("ram["));
write(m, i);
write(m, string'("] = "));
hwrite(m, my_ram(i));
writeline(output, m);
end loop;
wait for 1000 ns;
report "just kidding! end of testbench" severity failure;
end process;
end architecture;
Here you can see the output of the vhdl simulation is just x's even tough i loaded the memory...
## run all
ram[0] = XXX
ram[1] = XXX
ram[2] = XXX
ram[3] = XXX
ram[4] = XXX
ram[5] = XXX
ram[6] = XXX
ram[7] = XXX
ram[8] = XXX
ram[9] = XXX
ram[10] = XXX
ram[11] = XXX
ram[12] = XXX
ram[13] = XXX
ram[14] = XXX
Failure: just kidding! end of testbench
Time: 1010 ns Iteration: 0 Process: /sram/line__52 File: sram.vhd

Answer 1

This worked in vivado simulator for me:
-- FILE: ram_image.hex
-- ab
-- 12
-- ef
-- 14
-- 34
-- 23
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sram is
end entity;
architecture beh of sram is
constant sram_dw :integer := 8;
constant sram_aw :integer := 4;
constant sram_depth :integer := 2**sram_aw - 1;
type sram_t is array (0 to sram_depth-1) of std_logic_vector(sram_dw-1 downto 0);
shared variable my_ram :sram_t;
procedure hread_backport(
l :inout line;
value :out std_logic_vector
) is
variable offset :integer;
variable c :character;
variable good1 :boolean;
variable hex_val :std_logic_vector(3 downto 0);
begin
offset := 0;
value := (others => '0');
while (offset < value'high) loop
read(l, c, good1);
if (not good1) then exit; end if;
case c is
when '0' => hex_val := "0000";
when '1' => hex_val := "0001";
when '2' => hex_val := "0010";
when '3' => hex_val := "0011";
when '4' => hex_val := "0100";
when '5' => hex_val := "0101";
when '6' => hex_val := "0110";
when '7' => hex_val := "0111";
when '8' => hex_val := "1000";
when '9' => hex_val := "1001";
when 'A' | 'a' => hex_val := "1010";
when 'B' | 'b' => hex_val := "1011";
when 'C' | 'c' => hex_val := "1100";
when 'D' | 'd' => hex_val := "1101";
when 'E' | 'e' => hex_val := "1110";
when 'F' | 'f' => hex_val := "1111";
when others =>
hex_val := "XXXX";
assert false report "Found non-hex character'" & c & "'";
end case;
value( (value'high-offset) downto (value'high-offset-3) ) := hex_val;
offset := offset + 4;
end loop;
end procedure;
procedure sram_load_hex(filepath :string) is
file f :text;
variable b, m :line;
variable good :boolean;
begin
write(m, string'("opening file: ") & filepath );
writeline(output, m);
file_open(f, filepath, read_mode);
for i in sram_t'range loop
if (endfile(f)) then exit; end if;
readline(f, b);
hread_backport(b, my_ram(i));
end loop;
end procedure;
procedure sram_print_hex is
variable m :line;
begin
for i in sram_t'range loop
write(m, string'("read ram["));
write(m, i);
write(m, string'("] = "));
hwrite(m, my_ram(i));
writeline(output, m);
end loop;
end procedure;
begin
process
begin
sram_load_hex("C:/Users/racerx/Desktop/sandbox/sram/ram_image.hex");
wait;
end process;
process
begin
wait for 1000 ns;
sram_print_hex;
report "just kidding! end of testbench" severity failure;
end process;
end architecture;