Unable to output data from ram memory address - vhdl

Question

I am trying to build a ram in vhdl and in the below code I am successful in storing data in the ram locations 0000 and 0001. I am not successful in outputting the data from memory locations 0000 and 0001.
The following code is for the ram vhdl.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector(3 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end entity ram;
architecture RTL of ram is
type ram_type is array (0 to 15) of std_logic_vector(datain'range);
signal ram_comp : ram_type;
signal read_address : std_logic_vector(address'range);
begin
RamProc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram_comp(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process RamProc;
dataout <= ram_comp(to_integer(unsigned(read_address)));
end architecture RTL;
The following code is a testbench for the ram vhdl code.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity ram_tb is
end entity;
architecture behave of ram_tb is
component ram
port(
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector(3 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end component;
signal clock, we : std_logic;
signal datain, dataout : std_logic_vector(7 downto 0);
signal address : std_logic_vector(3 downto 0);
constant T : time := 20 ns;
begin
clock_process : process
begin
clock <= '0';
wait for T/2;
clock <= '1';
wait for T/2;
end process;
stim_process : process
begin
address <= "0000";
datain <= "00001111";
we <= '1';
wait for 20 ns;
address <= "0001";
datain <= "00001100";
wait for 20 ns;
we <= '0';
wait for 20 ns;
address <= "0000";
wait for 20 ns;
address <= "0001";
wait for 20 ns;
assert false report "Reached end of test";
wait;
end process;
end behave;
Simulation of the ram_tb screenshot
How can I output the data from address 0000 and 0001 on the dataout signal?
I tried the simulation on ModelSim below is the result of the simulation
the output is working fine. How is this possible?

Answer 1

In the testbench code the port map must be added.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity ram_tb is
end entity;
architecture behave of ram_tb is
component ram
port(
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector(3 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0)
);
end component;
signal clock, we : std_logic;
signal datain, dataout : std_logic_vector(7 downto 0);
signal address : std_logic_vector(3 downto 0);
constant T : time := 20 ns;
begin
uut: ram port map(clock, we, address, datain, dataout);
clock_process : process
begin
clock <= '0';
wait for T/2;
clock <= '1';
wait for T/2;
end process;
stim_process : process
begin
address <= "0000";
datain <= "00001111";
we <= '1';
wait for 20 ns;
address <= "0001";
datain <= "00001100";
wait for 20 ns;
we <= '0';
wait for 20 ns;
address <= "0000";
wait for 20 ns;
address <= "0001";
wait for 20 ns;
assert false report "Reached end of test";
wait;
end process;
end behave;