Beginner with Spartan 6, syntax issue - vhdl

Question

I'm writing a simple program using Spartan 6 for signed numbers but this error pops up says :hdl 806"near line 12 syntax error"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Multiplier_Top is
Port (
A : in signed (15 downto 0);
B : in signed (15 downto 0);
Sum : out signed (15 downto 0);
Overflow : out STD_LOGIC;
);
end Multiplier_Top;
architecture Behavioral of Multiplier_Top is
signal Sum_Int signed (16 downto 0) :=(others=>'0');
begin
Sum_Int <= Resize(A,17) + B;
Sum <= Sum_Int(15 downto 0);
Overflow <= Sum_Int(16) xor Sum_Int(15);
end Behavioral;

Answer 1

There are 2 syntax error in the design:
Line 11: Remove the ; after out STD_LOGIC; so it becomes out std_logic
Line 17: Insert a : in Sum_Int signed so it becomes Sum_Int : signed
Some other comments:
Line 17: Remove default value assign :=(others=>'0'), since that is not required when output is assigned by continuous assignment in line 21
Line 17 and others: Use VHDL attributes line 'length to avoid constants in code
The code can then look like this:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Multiplier_Top is
port (
A : in signed (15 downto 0);
B : in signed (15 downto 0);
Sum : out signed (15 downto 0);
Overflow : out std_logic
);
end Multiplier_Top;
architecture Behavioral of Multiplier_Top is
signal Sum_Int : signed (A'length downto 0); -- Length one bit more than A, assuming same length as B
begin
Sum_Int <= Resize(A, Sum_Int'length) + B;
Sum <= Sum_Int(Sum'range);
Overflow <= Sum_Int(Sum_Int'left) xor Sum_Int(Sum_Int'left - 1);
end Behavioral;