I am trying to make my BASYS 3 board (xc7a35tcpg236-1) take a 4-bit input via switches and show the respective hexadecimal character on the 7-segment display.
I, however, keep getting the following error, "[Common 17-165] Too many positional options when parsing '255/ECE255Lab5-2/ECE255Lab5-2.srcs/utils_1/imports/synth_1/Display.dcp', please type 'read_checkpoint -help' for usage info."
I am not sure how to fix this and I have not been able to find a solution, so any help would be greatly appreciated.
VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity Display is
Port ( --clk : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board
Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
LED_out : out STD_LOGIC_VECTOR (6 downto 0);-- Cathode patterns of 7-segment display
sw : in STD_logic_vector(3 downto 0));
end Display;
architecture Behavioral of Display is
begin
process(sw)
begin
anode_activate <= "0000";
case sw is
when "0000" => LED_out <= "0000001"; -- "0"
when "0001" => LED_out <= "1001111"; -- "1"
when "0010" => LED_out <= "0010010"; -- "2"
when "0011" => LED_out <= "0000110"; -- "3"
when "0100" => LED_out <= "1001100"; -- "4"
when "0101" => LED_out <= "0100100"; -- "5"
when "0110" => LED_out <= "0100000"; -- "6"
when "0111" => LED_out <= "0001111"; -- "7"
when "1000" => LED_out <= "0000000"; -- "8"
when "1001" => LED_out <= "0000100"; -- "9"
when "1010" => LED_out <= "0000010"; -- a
when "1011" => LED_out <= "1100000"; -- b
when "1100" => LED_out <= "0110001"; -- C
when "1101" => LED_out <= "1000010"; -- d
when "1110" => LED_out <= "0110000"; -- E
when "1111" => LED_out <= "0111000"; -- F
when others => NULL;
end case;
end process;
end Behavioral;
XDC:
set_property PACKAGE_PIN W4 [get_ports {Anode_Activate[3]}]
set_property PACKAGE_PIN V4 [get_ports {Anode_Activate[2]}]
set_property PACKAGE_PIN U4 [get_ports {Anode_Activate[1]}]
set_property PACKAGE_PIN U2 [get_ports {Anode_Activate[0]}]
set_property PACKAGE_PIN W7 [get_ports {LED_out[6]}]
set_property PACKAGE_PIN W6 [get_ports {LED_out[5]}]
set_property PACKAGE_PIN U8 [get_ports {LED_out[4]}]
set_property PACKAGE_PIN V8 [get_ports {LED_out[3]}]
set_property PACKAGE_PIN U5 [get_ports {LED_out[2]}]
set_property PACKAGE_PIN V5 [get_ports {LED_out[1]}]
set_property PACKAGE_PIN U7 [get_ports {LED_out[0]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
The problem had to do with a file being generated in the Utility folder. I have no idea why it was there, but the bitstream generated perfectly after I deleted everything in the Utility folder.
Related
Hello i have a Basys3 FPGA board. But i can't see SDA and SCL pins in XDC. Which pins should I use? I am using these pins. But data is not flowing. I would be glad if you help.
##Pmod Header JA
set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {SDA}];#Sch name = JA1
set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {SCL}];#Sch name = JA2
I'm doing a university assignment where a code was given from an old board and i had to run it on a new one. (Nexys --> Basys3). In one of the tasks, it was necessary to make the seven segment count to 9 (0-1-2-3-4-5-6-7-8-9) and then back to 0 (9-8-7-6-5-4-3-2-1-0). I did this task, but the teacher did not like exacly how it counts. It was something like (0-1-2-3-4-5-6-7-8-9 -> 9-8-7-6-5-4-3-2-1-0-0-1...) but should be (...1-0-1...).
And one more task is that with each new digit, the little dot should change it value (0 <--> 1)
I honestly do not fully understand the VHDL syntax,. which makes it much more difficult.
So my questions are:
At the moment i cannot understand why i have this additional "0" when counting...and how can i fix this ?
How to make little dot change it's value so it "blinks" ?
Yes, i know that you should simply change the value of correct bit something like...seg(7) <= '1'; but for some reason even this doesn't work...or again i do not fully understand something.
Code:
.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Nexysdemo is
Port (
clk : in std_logic;
btn : in std_logic_vector(3 downto 0);
sw : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0); -- Cathode patterns of 7-segment
an : out std_logic_vector(3 downto 0); --4 Anode signals
seg : out std_logic_vector(7 downto 0));
end Nexysdemo;
architecture Behavioral of Nexysdemo is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal clkdiv : std_logic_vector(24 downto 0); -- 24 downto 0
signal cntr : std_logic_vector(4 downto 0); -- 3 downto 0
signal cclk : std_logic;
signal dig : std_logic_vector(6 downto 0);
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
led <= sw;
dig <=
"0111111" when cntr = "00000" else --0
"0000110" when cntr = "00001" else --1
"1011011" when cntr = "00010" else --2
"1001111" when cntr = "00011" else --3
"1100110" when cntr = "00100" else --4
"1101101" when cntr = "00101" else --5
"1111101" when cntr = "00110" else --6
"0000111" when cntr = "00111" else --7
"1111111" when cntr = "01000" else --8
"1101111" when cntr = "01001" else --9
"1111111" when cntr = "01010" else --8
"0000111" when cntr = "01011" else --7
"1111101" when cntr = "01100" else --6
"1101101" when cntr = "01101" else --5
"1100110" when cntr = "01110" else --4
"1001111" when cntr = "01111" else --3
"1011011" when cntr = "10000" else --2 A
"0000110" when cntr = "10001" else --1 B
"0111111" when cntr = "10010" else --0 C
"0000000";
seg(6 downto 0) <= not dig;
an <= btn;
seg(7) <= '1';
-- Divide the master clock (100Mhz) down to a lower frequency.
process (clk)
begin
if clk = '1' and clk'Event then
clkdiv <= clkdiv + 1;
end if;
end process;
cclk <= clkdiv(24); --24
process (cclk)
begin
if cclk = '1' and cclk'Event then
if cntr = "10010" then --1001
cntr <= "00000";
else
cntr <= cntr + 1;
end if;
end if;
end process;
end Behavioral;
Basys-3-Master.xdc
# Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
##7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN V7 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports {btn[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
set_property PACKAGE_PIN T18 [get_ports {btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
set_property PACKAGE_PIN W19 [get_ports {btn[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
set_property PACKAGE_PIN T17 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
I am trying to write code for my Nexys 4 DDR to display 4 digits which are chosen from a keypad.
They keypad is fed into port JA and then decoded and displayed on the seven segment displays. The numbers are supposed to shift left after a new key is pressed.
As of now, my code is generating a bitstream but the displays only show 0's and the reset button seems to be functioning. I'm not sure if this is a clock issue or an inconsistency somewhere in my code?
I've attached my design sources and my constraint file.
Thanks.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;
entity PmodKYPD_Nexsy4 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
JA : inout STD_LOGIC_VECTOR (7 downto 0); -- PmodKYPD connected to Pmod JA
an : out STD_LOGIC_VECTOR (7 downto 0); -- Controls which position of the 8 seven segment displays to display
seg: out STD_LOGIC_VECTOR (6 downto 0)); -- digit to display on seven segment display
end PmodKYPD_Nexsy4;
architecture Behavioral of PmodKYPD_Nexsy4 is
component DisplayController is
Port ( DispVal : in STD_LOGIC_VECTOR (15 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
segOut : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal Decode: STD_LOGIC_VECTOR (3 downto 0);
signal RegLast : STD_LOGIC_VECTOR (15 downto 0);
signal refresh : STD_LOGIC_VECTOR (19 downto 0);
signal LEDAct : std_logic_vector(1 downto 0);
signal Row : STD_LOGIC_VECTOR (3 downto 0);
signal Col : STD_LOGIC_VECTOR (3 downto 0);
signal sclk :STD_LOGIC_VECTOR(19 downto 0);
signal DecodeOut : STD_LOGIC_VECTOR (3 downto 0);
signal Reg : unsigned(15 downto 0) := (others => '0');
begin
Row <= JA(7 downto 4);
Col <= JA(3 downto 0);
process(clk,reset)
begin
if(reset='1') then
refresh <= (others => '0');
elsif(rising_edge(clk)) then
refresh <= refresh + 1;
end if;
end process;
LEDAct <= refresh(19 downto 18);
process(clk)
begin
if clk'event and clk = '1' then
-- 1ms
if sclk = "00011000011010100000" then
--C1
Col<= "0111";
sclk <= sclk+1;
-- check row pins
elsif sclk = "00011000011010101000" then
--R1
if Row = "0111" then
DecodeOut <= "0001"; --1
--R2
elsif Row = "1011" then
DecodeOut <= "0100"; --4
--R3
elsif Row = "1101" then
DecodeOut <= "0111"; --7
--R4
elsif Row = "1110" then
DecodeOut <= "1111"; --F (mod from "0000"; --0)
end if;
sclk <= sclk+1;
-- 2ms
elsif sclk = "00110000110101000000" then
--C2
Col<= "1011";
sclk <= sclk+1;
-- check row pins
elsif sclk = "00110000110101001000" then
--R1
if Row = "0111" then
DecodeOut <= "0010"; --2
--R2
elsif Row = "1011" then
DecodeOut <= "0101"; --5
--R3
elsif Row = "1101" then
DecodeOut <= "1000"; --8
--R4
elsif Row = "1110" then
DecodeOut <= "0000"; --0 (mod from "1111"; --F)
end if;
sclk <= sclk+1;
--3ms
elsif sclk = "01001001001111100000" then
--C3
Col<= "1101";
sclk <= sclk+1;
-- check row pins
elsif sclk = "01001001001111101000" then
--R1
if Row = "0111" then
DecodeOut <= "0011"; --3
--R2
elsif Row = "1011" then
DecodeOut <= "0110"; --6
--R3
elsif Row = "1101" then
DecodeOut <= "1001"; --9
--R4
elsif Row = "1110" then
DecodeOut <= "1110"; --E
end if;
sclk <= sclk+1;
--4ms
elsif sclk = "01100001101010000000" then
--C4
Col<= "1110";
sclk <= sclk+1;
-- check row pins
elsif sclk = "01100001101010001000" then
--R1
if Row = "0111" then
DecodeOut <= "1010"; --A
--R2
elsif Row = "1011" then
DecodeOut <= "1011"; --B
--R3
elsif Row = "1101" then
DecodeOut <= "1100"; --C
--R4
elsif Row = "1110" then
DecodeOut <= "1101"; --D
end if;
sclk <= "00000000000000000000";
else
sclk <= sclk+1;
end if;
end if;
end process;
SHIFT_REG : process(clk)
variable tmp : unsigned(15 downto 0);
begin
if clk'event and clk = '1' then
tmp := Reg;
tmp := tmp sll 4;
tmp(3 downto 0) := unsigned(DecodeOut);
Reg <= tmp;
end if;
end process;
C0: DisplayController port map (DispVal=>STD_LOGIC_VECTOR(Reg), Selector=>LEDAct, anode=>an, segOut=>seg );
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DisplayController is
Port ( DispVal : in STD_LOGIC_VECTOR (15 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
segOut : out STD_LOGIC_VECTOR (6 downto 0));
end DisplayController;
architecture Behavioral of DisplayController is
begin
process(Selector)
begin
case Selector is
when "00" =>
anode <= "11110111";
-- activate LED1 and Deactivate LED2, LED3, LED4
-- the first hex digit of the 16-bit number
case DispVal(15 downto 12) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "01" =>
anode <= "11111011";
-- activate LED2 and Deactivate LED1, LED3, LED4
-- the second hex digit of the 16-bit number
case DispVal(11 downto 8) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "10" =>
anode <= "11111101";
-- activate LED3 and Deactivate LED2, LED1, LED4
-- the third hex digit of the 16-bit number
case DispVal(7 downto 4) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
when "11" =>
anode <= "11111110";
-- activate LED4 and Deactivate LED2, LED3, LED1
-- the fourth hex digit of the 16-bit number
case DispVal(3 downto 0) is -- active low to display segment
when "0000" => SegOut <= "1000000"; --0
when "0001" => SegOut <= "1111001"; --1
when "0010" => SegOut <= "0100100"; --2
when "0011" => SegOut <= "0110000"; --3
when "0100" => SegOut <= "0011001"; --4
when "0101" => SegOut <= "0010010"; --5
when "0110" => SegOut <= "0000010"; --6
when "0111" => SegOut <= "1111000"; --7
when "1000" => SegOut <= "0000000"; --8
when "1001" => SegOut <= "0010000"; --9
when "1010" => SegOut <= "0001000"; --A
when "1011" => SegOut <= "0000011"; --B
when "1100" => SegOut <= "1000110"; --C
when "1101" => SegOut <= "0100001"; --D
when "1110" => SegOut <= "0000110"; --E
when "1111" => SegOut <= "0001110"; --F
when others => Segout <= "0111111";
end case;
end case;
end process;
end Behavioral;
## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { seg[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { seg[1] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
##Buttons
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L9P_T1_DQS_14 Sch=btnc
##Pmod Header JA
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
So, I've designed a 2-bit Full Adder, made up of Full Adders and Half Adders. I just started using Vivado's I/O Planning tool for the port to pin assignments, but I've run into a problem. One of my inputs, the initial carry_in for the first bit, I want set to ground since it should always be 0. I know I could just force it to 0 in my VHDL code, but I'm told that's not really the proper way to do it. I tried to set that port to one of the ground pins in the i/o planner but Vivado just tells me I can't place a terminal in an empty pin location. Anyone know how to do this?
As a temporary solution, I just assigned the carry_in port to a button input that I'll leave unpressed so it will always be 0. Everything works as it should when it's programmed onto the board.
*Using Vivado 2015.2 and working on the ZYBO Development Board.
Here's the top level 2-bit Full Adder Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity full_adder_2bit is
port(
a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
carry_in : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (1 downto 0);
carry_out : out STD_LOGIC
);
end full_adder_2bit;
architecture structural of full_adder_2bit is
component full_adder is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
carry_in : in STD_LOGIC;
sum : out STD_LOGIC;
carry_out : out STD_LOGIC
);
end component;
signal cin_fa1 : std_logic;
begin
fa0: full_adder port map (a => a(0), b => b(0), carry_in => carry_in, sum => sum(0), carry_out => cin_fa1);
fa1: full_adder port map (a => a(1), b => b(1), carry_in => cin_fa1, sum => sum(1), carry_out => carry_out);
end structural;
And here's what I've got for constraints from the I/O planner. It all works fine, I just want to set the carry_in to ground instead of an unused button.
set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sum[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sum[0]}]
set_property PACKAGE_PIN T16 [get_ports {a[1]}]
set_property PACKAGE_PIN P15 [get_ports {a[0]}]
set_property PACKAGE_PIN W13 [get_ports {b[1]}]
set_property PACKAGE_PIN G15 [get_ports {b[0]}]
set_property PACKAGE_PIN M15 [get_ports {sum[1]}]
set_property PACKAGE_PIN M14 [get_ports {sum[0]}]
set_property PACKAGE_PIN D18 [get_ports carry_out]
set_property IOSTANDARD LVCMOS33 [get_ports carry_out]
set_property PACKAGE_PIN Y16 [get_ports carry_in]
set_property IOSTANDARD LVCMOS33 [get_ports carry_in]
You could assign it to an unused, unconnected pin and put activate the internal pulldown on it.
However, it's better to tie it to '0' in your VHDL file. The comment "it's not the proper way to do it" is somewhat debatable. A full adder entity should really have the carry_in input. However, a FPGA toplevel should really only have the pins it requires.
The better way to do it would be to have a file (let's say, toplevel.vhd) that instantiates a full_adder_2bit tying the carry-in to '0'. That way, full_adder_2bit keeps it useful carry_in bit and your toplevel is rid of unecessary pin.
I'm trying to move a robot arm via FPGA board. The communication is working just fine but I want to make an automated sequence that I would be able to modify on fly. Basically what I need is to be able to code sequentially what follows:
PA0 <= PA1; (for 2s)
PA2 <= PA5; (for 3,5s)
PA4 <= PA3; (for 3s)
PA2 <= PA1; (for 2s)
in a form of data vector or in a case block just to keep it simple and be able to add/change signals and time for which those signals will be propagated.
I've tried this with simple timer and if statements but it's nowhere near perfect and I'm not able to change signal's propagation time without conversing it to binary and adding to existing time counter. It simply looks messy. And I can't change states in case based on time passed.
EDIT:
As asked I'm including piece of code with declarations (LEDs are just for tests).
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity abra is
port
(
PA0 : out std_logic ;
PA2 : out std_logic;
PA4 : out std_logic;
PA6 : out std_logic;
PA1 : in std_logic;
PA3 : in std_logic;
PA5 : in std_logic;
PA7 : in std_logic;
LED: out std_logic_vector(7 downto 0);
RST: in std_logic; --ROT_CENTER--
CLK : in std_logic --50MHz clock--
);
end abra;
architecture Behavioral of abra is
signal TIME_COUNTER : std_logic_vector (31 downto 0) := (others => '0');
signal CNTR : std_logic_vector (7 downto 0) := (others => '0');
begin
control: process(CLK)
begin
if rising_edge(CLK) then
if(TIME_COUNTER = b"00000000101111101011110000100000") then
CNTR <= CNTR + 1; --should inc every 1s--
TIME_COUNTER <= (others => '0');
else
TIME_COUNTER <= TIME_COUNTER + 1;
end if;
if( RST = '1' ) then
CNTR <= (others => '0');
LED <= "11111111";
end if;
PA0 <= '0';
PA2 <= '0';
PA4 <= '0';
PA6 <= '0';
-----------------
if( CNTR >= "00000000" AND CNTR < "00000100") then
PA6 <= PA5; --servo 1 / side up--
LED <= b"00000001";
end if;
if( CNTR >= "00000100" AND CNTR < "00001011") then
PA4 <= PA3; --servo 3 / side down--
LED <= b"00000010";
end if;
if( CNTR >= "00001011" AND CNTR < "00110000") then
PA2 <= PA1; -- servo 6 / side down--
LED <= b"00000100";
end if;
if ( CNTR >= "00100000") then
LED <= b"00000000";
end if;
------------------
end if;
end process control;
end Behavioral;
UCF declarations:
NET "PA0" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA2" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA4" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA6" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA1" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA3" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA5" LOC = "A17" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "PA7" LOC = "B17" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "RST" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
NET "CLK" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "LED<0>" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<1>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<2>" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<3>" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<4>" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<5>" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<6>" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;
NET "LED<7>" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | Drive = 8 ;