I am doing a university project in which i have to build a I2C which have only one slave and will have to transmit a data with 5 bits, 4 bits for the number which is in the range of 0 to 9 and 1 bit to read or write, i'm using a DE10-LITE with VHDL for this project, which has a 50 Mhz default clock, i was looking into the "ALTPLL" inside quartus prime but i can't find the option to set my clock to 100kbps, i did find in the in some forums that the "Set up PLL in LVDS mode" enables that, but for some reason quartus won't let me activate it. My SDA will be 100kbps, and the SCL 50mhz.
As the Other people have said: You don't need a PLL for that. If you already have a default clock of 50MHz then you just need to divide that by 500, using a counter, and then you have your 100kHz clock.
Anyways, you would want to start the counter only when there is a request on the bus. So user16145658 is correct: The generated clock should be the output of your state machine.
You don't need to change the clock of the FPGA, since you are using an FPGA, you only need to implement an i2c core to communicate with the i2c device.
And the i2c specification specifies the rate of i2c
Standard mode (Sm) 100 kbit/s
Fast mode (Fm) 400 kbit/s
Related
Good morning I need to perform a 0.4 Hz pwm and with LEDC I can only reach 1 hz in esp32. Could you tell me if there is a possibility to do it?
I assume you are currently using the functions from some esp32 library. Like in the Arduino world, there is another way. You can set the right Bits so you manually create a PWM signal. Here is the Technical Reference Manual:
https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
You will find all the relevant Information in chapter 14 (LED_PWM).
I have an Arduino Uno R3 (actually, distributed from Elegoo but has the same exact components) and I thought about burning the ATMega 8 chip on it with a bootloader, using the "Arduino as ISP" feature on the Arduino IDE.
I looked at the specs for the ATMega 8 chip, and I would like to just ask - everywhere I've looked online, it says the default CPU clock speed is 16MHz, which makes sense because of the crystal clock onboard running at 16MHz. However, I'm not sure the code I have already written is safe:
#define SPI_CLOCK (16000000/6) // Internal clock speed 16 MHz for Arduino UNO.
I think that this code will be fine considering the specs. The example told me to set SPI_CLOCK to a value of 1000000/6, which slow enough for an ATtiny85 (# 1 MHz), but since I want to use the full functionality of the crystal I have onboard and want a faster clock speed, is it safe to set SPI_CLOCK directly to 16000000/6?
Any help will be appreciated.
Thanks!
Anyways, AterLux answered my question:
Setting SPI clock speed on the programmer only affects how fast you can flash the device. It does not change how the flashed code works – AterLux
I want to use hdmi monitor with cyclone V GX board, but I don't get an acknowledgement from adv7513 on i2c bus.
I think there is a problem with the address that I am sending at the beginning of the i2c transaction (I get no acknowledgement of address) I couldn't find information on whether PD/AD is low or high. Also I am not sure if i should use 7 or 8 bit address, so I would like some explanation.
I used i2c controller that i found online:
https://www.digikey.com/eewiki/pages/viewpage.action?pageId=10125324
signaltap result
I assume you haven't read the ADV7513 Programming Guide
The ADV7513 uses four I2C register maps. The SDA/SCL programming
address for the Main Register Map is 0x72 or 0x7A, based on whether
PD/AD is pulled high (10KΩ resistor to power supply = 0x7A) or pulled
low (10KΩ resistor to GND = 0x72) when power is applied to the
supplies. The user should wait 200ms for the address to be decided,
after the power supplies are high, before attempting to communicate
with the ADV7513 using I2C
I2C addresses are 7-bit or 10-bit not 8-bit. In this case it is 7-bit.
See I2C Specification. So if PD/AD is high, 7-bit address is 0x7A. In binary your 7 bits will be: 1111010. The R/W bit is the last bit of the first I2C 'address' byte but the vhd code you posted doesn't need that as part of the address, that's done separately.
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
If you are still having problems, check your pull-ups, I2C SCL clock rate, ensure the master allows clock stretching. The VHDL code you posted has quite a lot of information about how to use so re-read that.
Alternatively take to question to Electrical Engineering Stack Exchange and take some oscilloscope readings of SDA/SCL.
I need develope synthesizable custom verilog code for generating a higher frequency clock from low frequency clock i.e from 50 MHz clock i need to generate 100 MHZ clock . kindly help how to do the same.
A pure Verilog solution is not stable, so dedicated FPGA resources must be used.
Please see this previous answer; it applies to Verilog also, even through tagged VHDL.
My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks internally but how does a 50mhz clock produce a 62mhz clock which is higher !?
in Xilinx Spartan devices you can use so called DCMs (digital clock managers) that give you a whole lot of possibilities; see Spartan User Guide or Xilinx Spartan 3 DCM. with the synthesizer option, clock multiplication/division is possible.
There are built in technologies that multiply the clock to higher frequencies. See Frequency Multiplier and Phase Locked Loop
under your design name in Implementation window in ISE right click and add new sorce select IPcore then select clocking wizard you can enter the primary freq : 50 mhz and required out freq: 62 mhz and the core generator will do it for you.