Mysterious bit mismatch for VHDL - vhdl

Question

I am making a 32 bit register with port and generic mapping. For some reason it says that the target signal Qt has 31 bits, while the input has 32 bits. Makes no sense right now. I looked through everything, and could not find how the Qt could be anything else than 32 bits since I declared the signal as signal Qt: std_logic_vector(31 downto 0);Any help is appreciated thanks.
I isolated the error line Qt <= D; and it still threw an exception. Down below is my minimally reproducible example.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;

Answer 1

Did not realize that I had N: INTEGER:= 31 in the top file. When I changed the definition to N: INTEGER:= 32 the error disappeared. Sloppy coding on my part. I don't know why the tcl referenced this in the register file and not the top(lapfn) file. Is this because VHDL is written top down after port mapping, and it assumed the component from the top was the true bit-size?
entity LAPfn is
Port (resetn, clock, sclr, lap_db: in std_logic;
lap_select: in std_logic_vector (2 downto 0);
Data_in: in std_logic_vector (31 downto 0);
Lap_bits: out std_logic_vector (31 downto 0);
zlap: out std_logic;
cout: out std_logic_vector(2 downto 0));
end LAPfn;
architecture Behavioral of LAPfn is
component my_rege
generic (N: INTEGER:= 31);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;