Can you import a vhdl package in a systemverilog file? - vhdl

Question

Can you import a vhdl package in a systemverilog file?
Let's say I have a VHDL package:
library ieee;
use ieee.std_logic_1164.all;
-- FILE: my_pkg.vhd
package my_pkg is
type type1 is record
sig2 : std_logic;
vec1 : std_logic_vector(7 downto 0);
end record;
end package;
Can I use it in a System Verilog file like this:
// FILE: testbench.sv
import my_pkg::*;
module testbench;
type1 sigtype1;
initial begin
sigtype1.sig2 = 1'b1;
sigtype1.vec1 = 8'hA;
$finish(2);
end
endmodule
would this generate a syntax error or would it imply the equivalent systemverilog package:
// FILE: my_pkg.sv
package my_pkg;
typedef struct packed {
bit sig2;
bit [7:0] vec1;
};
endpackage;
Here's my simulator output:
C:\questasim64_2020.4\win64\vcom.exe -2002 -l simout.vhdl.log
-work work ./hdl/my_pkg.vhd
QuestaSim-64 vcom 2020.4 Compiler 2020.10 Oct 13 2020
Start time: 11:39:52 on Jan 19,2022
vcom -2002 -l simout.vhdl.log -work work ./hdl/my_pkg.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling package my_pkg
End time: 11:39:52 on Jan 19,2022, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
ok
C:\questasim64_2020.4\win64\vlog.exe -work work -l simout.vlog.log
./hdl/testbench.sv
QuestaSim-64 vlog 2020.4 Compiler 2020.10 Oct 13 2020
Start time: 11:39:52 on Jan 19,2022
vlog -work work -l simout.vlog.log ./hdl/testbench.sv
** Error:
C:/Users/wpmoore/Desktop/collins/sandbox/sandbox.try1/hdl/testbench.sv(
2): (vlog-13006) Could not find the package (my_pkg). Design read will
continue, but expect a cascade of errors after this failure.
Furthermore if you experience a vopt-7 error immediately before this
error then please check the package names or the library search paths
on the command line.
End time: 11:39:52 on Jan 19,2022, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

Answer 1

I am only aware of one tool, Modelsim/Questa that allows sharing of packages between SystemVerilog and VHDL, and only for the sharing of data types/typedefs across these languages. The most useful purpose being connecting ports between mixed language instances with a shared data type.
Look for the -mixedsvvh switch in the Questa User Manual.

Answer 2

Short answer 'No'.
If you can get your simulator to compile a VHDL module you may well be able to instantiate it in a Verilog / SV module, and vice versa. Although you are mixing languages here it is fairly unambiguous how the simulator should connect these. However because they are different languages it is not defined how code written in both should interact with each other. Certainly I would not expect any VHDL packages to be usable in Verilog/SV. Can you migrate the contents to SV? Or perhaps create a tool to generate two files equivalent VHDL and SV?