VHDL if statement - Syntax error near text - vhdl

Can anyone see what is wrong with my code?
I get a error on the comment line. Saying syntax error near text. I tried to change from both binary to hex numbers, but keep getting the same error.
Were the errors are is comment selected.
This are the errors:
Error (10500): VHDL syntax error at MAL.vhd(26) near text
Error (10500): VHDL syntax error at MAL.vhd(26) near text ""; expecting "then"
Error (10500): VHDL syntax error at MAL.vhd(26) near text ­
Error (10500): VHDL syntax error at MAL.vhd(26) near text ¬
Error (10500): VHDL syntax error at MAL.vhd(29) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at MAL.vhd(31) near text "if"; expecting "process"
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY MAL IS
PORT (
clk_50 : IN std_logic;
pulse_out : OUT std_logic
);
END MAL;
ARCHITECTURE behave OF MAL IS
SIGNAL pulse : std_logic;
SIGNAL counter : std_logic_vector(15 DOWNTO 0);
BEGIN
PROCESS (clk_50) IS
BEGIN
pulse <= '0';
-- if counter = ‭x"‭C34F‬"‬ then
-- counter <= (others => '0');
pulse <= '1';
-- else
counter <= counter + 1;
END IF;
END PROCESS;
--output
pulse_out <= pulse;
END ARCHITECTURE behave;

You have some illegal character in there. Remove line 27 and re-write it and you should be ok.

Related

two different errors in modelsim when '=' or '<=' used

I'm learning VHDL, and I've been struggling with this simple example below since yesterday.
Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input. The system has three (3) output signals 'LOW' 'MID' and 'HIGH' that generate the following values:
Assume that all signals are of type Std_logic.
The code is like this;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY LMHcounter IS
PORT(clk,reset:in std_logic;
L:out std_logic;
M:out std_logic;
H:out std_logic);
END LMHcounter;
ARCHITECTURE behavior OF UPcounter IS
SIGNAL count:std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk,reset)
BEGIN
if reset='1' then count<="0000";
elsif (rising_edge(clk))then
if count<="1001" then
count<="0000";
else count<=count+"0001";
end if;
end if;
END PROCESS;
L<='1' when count<="0101";
else '0';
M<='1' when count="0110";
else '0';
H<='1' when count>="0111";
else '0';
END behavior;
If I use L='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): near "=": (vcom-1576) expecting == or '+' or '-' or '&'.
If I use L<='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): Illegal target for signal assignment.
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1136) Unknown identifier "L".
Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I can't use ':=' as apparently modelsim does not support
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1441) CONDITIONAL VARIABLE ASSIGNMENT is not defined for this version of the language.
** Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I'm sure it's trivial, but I can't seem to find an answer anywhere. And also can someone explain please what is happening in the background if I use '=' or '<='?
Thanks
There are quite a few errors i found,
Firstly, you are trying to describe an architecture for a different entity other than the one you declared. I guess that should be ARCHITECTURE behavior OF LMHcounterIS instead of ARCHITECTURE behavior OF UPcounter IS
The syntax for the conditional signal assignment is wrong, you should use it as
signal <= [expression when condition else ...] expression;. In your code that should be L<='1' when count<="0101" else '0';
M<='1' when count="0110" else '0';
H<='1' when count>="0111" else '0';

vhdl error in a for loop. Erro 10500

I'm doing a simple ula in vhdl. In the sum operation get a message error
Error:
Error (10500): VHDL syntax error at rjr_neander.vhd(30) near text "for"; expecting "end", or "(", or an identifier ("for" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at rjr_neander.vhd(34) near text "loop"; expecting ";", or an identifier ("loop" is a reserved keyword), or "architecture"
Code:
entity ula is
port(
inputA, inputB: in bit_vector(0 to 7);
output: out bit_vector(0 to 7)
);
end ula;
architecture sum8bits of ula is
signal cout : bit_vector(0 to 6);
begin
-- Half adder do bit 0
output(0) <= inputA(0) xor inputB(0);
cout(0) <= inputA(0) and inputB(0);
for indice in 1 to 7 loop
-- iteracao para fazer o full adder dos 7 bits restantes
output(indice) <= inputA(indice) xor inputB(indice) xor cout(indice-1);
cout(indice) <= (inputA(indice) and inputB(indice)) or (inputA(indice) and cout(indice-1)) or (inputB(indice) and cout(indice-1));
end loop;
end sum8bits;
What is my mistake?

vhdl error code 10500 for keywords already present

This code is for a PRBS (pseudo-random binary sequence) receiver. it is supposed to take three values and simulate a PRBS generator and check the obtained vales with the values generated.
But the code is showing errors for keywords like begin which are already present
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity receiver is
port(
inp : in std_logic;
clock : in std_logic;
count : out std_logic_vector(4 downto 0);
check : out std_logic);
end receiver;
architecture rec of receiver is
signal P : std_logic_vector(2 downto 0);
signal O : std_logic_vector(2 downto 0);
process (clock)
variable cnt : integer range 0 to 3;
begin
if clock'event and clock='1' then
P <= inp & P(2 downto 1);
cnt<=cnt+1;
end if;
if (cnt = 3) then
O<=P;
elseif (cnt >3)
O <= inp & O(2 downto 1);
end if;
if((O(2) xor O(0)) = P(0))
check <= '0';
else
check <= '1';
count <= count +1;
end if;
end process;
end rec;
Error (10500): VHDL syntax error at receiver.vhd(18) near text "process"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "and"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(24) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(25) near text "then"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(28) near text "O"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(29) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(31) near text "check"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
The structure of your entity needs to look like this:
entity receiver is
port (
-- Your ports
);
end receiver;
architecture rec of receiver is
-- Declarations here
begin -- ** Your code is missing this part
process (clock)
begin
-- your process
end process;
end rec;
As mentioned in the comments, always start with the first error you see; understand and solve that one first, and many later errors will normally go away as a result.
You have declared cnt as a variable, and then are trying to increment it using cnt <= cnt + 1;, but variables assignment should use := not <=.
The next error is your use of elseif; this is not a real keyword, and it looks like you wanted to use elsif. This line is also missing a then.
You then have a line if((O(2) xor O(0)) = P(0)), which is again missing a then.
Lastly, you are trying to directly increment count which is an out port. This is not possible, since you are trying to read an output in order to add one to it; there are a few ways to resolve this, but personally I would create an intermediate signal (e.g. count_s), which you use in your process, then assign your output to this signal with count <= count_s, somewhere outside the process.
With all these issues resolved, your code at least compiles.
As a side note, it would help you to have better vertical alignment of your code; your end process should vertically align with its opening process, and so on.

Need help VHDL in Xilinx

So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock signal. The code I developed was something like these (it was based on a schematic so the entity and architecture is supposed to remain untouched I think):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY projetesquema2_projetesquema2_sch_tb IS
END projetesquema2_projetesquema2_sch_tb;
ARCHITECTURE behavioral OF projetesquema2_projetesquema2_sch_tb IS
COMPONENT projetesquema2
PORT( CLOCK : IN STD_LOGIC;
ACL : IN STD_LOGIC;
CAT : OUT STD_LOGIC;
CRT : OUT STD_LOGIC;
CLT : OUT STD_LOGIC;
ACA : IN STD_LOGIC);
END COMPONENT;
SIGNAL CLOCK : STD_LOGIC;
SIGNAL ACL : STD_LOGIC;
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
BEGIN
UUT: projetesquema2 PORT MAP(
CLOCK => CLOCK,
ACL => ACL,
CAT => CAT,
CRT => CRT,
CLT => CLT,
ACA => ACA
);
*** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACA='0') then
CAT <= "0000";
else
CAT <= CAT + 1;
end if;
end if;
end process;
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACL='0') then
CLT <= "0000";
else
CLT <= CLT + 1;
end if;
end if;
end process;
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
*** End Test Bench - User Defined Section ***
END;
This gives me some errors that I don't know how to fix, hope somebody can actually help me.
Errors are:
ERROR:Line 54: Syntax error near "process".
ERROR:Line 55: Syntax error near "begin".
ERROR:Line 58: Type std_logic does not match with a string literal
ERROR:Line 60: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 68: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 70: Syntax error near "if".
ERROR:Line 77: Type std_logic does not match with a string literal
ERROR:Line 79: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 22: Unit ignored due to previous errors.
ERROR:Line 85: Syntax error near "WAIT".
Assuming the asterisk delimited comments aren't part of the VHDL design specification:
You have an extraneous PROCESS and BEGIN:
tb : PROCESS
BEGIN
process (CLOCK)
begin
There's an extra end if:
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
There are more extraneous statements:
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
This should simply be:
end Behavioral;
or
end architecture Behavioral;
And now we find semantic errors:
'CAT' is defined as a scalar std_logic:
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
and used in the component declaration for projetesquema2.
You can't promote it to a std_logic_vector value:
CAT <= "0000";
else
CAT <= CAT + 1;
or add an integer to it like it was declared as an unsigned (the use clause references package numeric_std, and BTW the unisim stuff can be dumped).
The same argument hold true for CRT and CLA. projetesquema appears to translate into English as project plan, there is insufficient information to advise an answerer how to fix these issues.
Perhaps if you made the entity and architecture for projetesquema2 available or told us what it does and what the port names mean?
It seems you've either been thrown in the deep end, missed part of your reading list or haven't been paying attention in class from the errors we see so far.
Stackoverflow may not where you should be going as a first resource for learning VHDL, and the Xilinx tools are somewhat unfriendly for error messages.
I know this it's in English but try this reference for an overview of VHDL.
Right around here you start defining a process inside a process, which isn't legal. Nor does it make much sense.
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then

Type error infix expression VHDL

I am coding a basic combinational circuit in VHDL, which has an AND gate with two inputs a and b. The output of this "t" is OR'ed with a negated input "c". This output "s" is then NAND with "a" to give the final output "d".
Here's the code.
library ieee;
use ieee.std_logic_1164.all;
entity logicgate is
port(a,b,c: in std_logic;
d: out std_logic);
end logicgate;
architecture arch_logicgate of logicgate is
begin
signal s: std_logic;
signal t: std_logic;
t<= a and b;
s<= (not c) or t;
d<= a nand s;
end arch_logicgate;
Transcript:
-- Compiling architecture arch_logicgate of logicgate
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s".
#
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting
I know I am missing out on the basics. Please help me out.
The first error message:
** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
arises because there are declarations in the execution region.
Put them in the declaration region, before begin
architecture arch_logicgate of logicgate is
signal s: std_logic;
begin
...

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