I'm learning VHDL, and I've been struggling with this simple example below since yesterday.
Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input. The system has three (3) output signals 'LOW' 'MID' and 'HIGH' that generate the following values:
Assume that all signals are of type Std_logic.
The code is like this;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY LMHcounter IS
PORT(clk,reset:in std_logic;
L:out std_logic;
M:out std_logic;
H:out std_logic);
END LMHcounter;
ARCHITECTURE behavior OF UPcounter IS
SIGNAL count:std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk,reset)
BEGIN
if reset='1' then count<="0000";
elsif (rising_edge(clk))then
if count<="1001" then
count<="0000";
else count<=count+"0001";
end if;
end if;
END PROCESS;
L<='1' when count<="0101";
else '0';
M<='1' when count="0110";
else '0';
H<='1' when count>="0111";
else '0';
END behavior;
If I use L='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): near "=": (vcom-1576) expecting == or '+' or '-' or '&'.
If I use L<='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): Illegal target for signal assignment.
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1136) Unknown identifier "L".
Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I can't use ':=' as apparently modelsim does not support
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1441) CONDITIONAL VARIABLE ASSIGNMENT is not defined for this version of the language.
** Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I'm sure it's trivial, but I can't seem to find an answer anywhere. And also can someone explain please what is happening in the background if I use '=' or '<='?
Thanks
There are quite a few errors i found,
Firstly, you are trying to describe an architecture for a different entity other than the one you declared. I guess that should be ARCHITECTURE behavior OF LMHcounterIS instead of ARCHITECTURE behavior OF UPcounter IS
The syntax for the conditional signal assignment is wrong, you should use it as
signal <= [expression when condition else ...] expression;. In your code that should be L<='1' when count<="0101" else '0';
M<='1' when count="0110" else '0';
H<='1' when count>="0111" else '0';
Related
I'm currently programming a system in VHDL, and I'm using an enumerator from another package called vnir, which is defined as such:
package vnir is
type row_type_t is (ROW_NONE, ROW_NIR, ROW_BLUE, ROW_RED);
end package vnir;
I've defined my architecture as such
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
The internal signal vnir_row_ready_i can be assigned to no problem, however the relational operator doesn't seem to work as ModelSim throws this error when I try to compile:
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): (vcom-1581) No feasible entries for infix operator '/='.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): Type error resolving infix expression "/=" as type std.STANDARD.BOOLEAN.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(28): VHDL Compiler exiting
My coworker helped me figure out how to make it work! I think that the /= operator is created in the vnir scope, but not ported over to the entity I'm working on. By writing :use work.vnir."/="; at the beginning of the file it compiles, so the full entity looks like so:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
use work.vnir."/=";
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
Alternatively it did work by including use work.vnir.all; and taking out the vnir. before the types, but that wasn't possible with the project I'm working one
So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock signal. The code I developed was something like these (it was based on a schematic so the entity and architecture is supposed to remain untouched I think):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY projetesquema2_projetesquema2_sch_tb IS
END projetesquema2_projetesquema2_sch_tb;
ARCHITECTURE behavioral OF projetesquema2_projetesquema2_sch_tb IS
COMPONENT projetesquema2
PORT( CLOCK : IN STD_LOGIC;
ACL : IN STD_LOGIC;
CAT : OUT STD_LOGIC;
CRT : OUT STD_LOGIC;
CLT : OUT STD_LOGIC;
ACA : IN STD_LOGIC);
END COMPONENT;
SIGNAL CLOCK : STD_LOGIC;
SIGNAL ACL : STD_LOGIC;
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
BEGIN
UUT: projetesquema2 PORT MAP(
CLOCK => CLOCK,
ACL => ACL,
CAT => CAT,
CRT => CRT,
CLT => CLT,
ACA => ACA
);
*** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACA='0') then
CAT <= "0000";
else
CAT <= CAT + 1;
end if;
end if;
end process;
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACL='0') then
CLT <= "0000";
else
CLT <= CLT + 1;
end if;
end if;
end process;
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
*** End Test Bench - User Defined Section ***
END;
This gives me some errors that I don't know how to fix, hope somebody can actually help me.
Errors are:
ERROR:Line 54: Syntax error near "process".
ERROR:Line 55: Syntax error near "begin".
ERROR:Line 58: Type std_logic does not match with a string literal
ERROR:Line 60: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 68: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 70: Syntax error near "if".
ERROR:Line 77: Type std_logic does not match with a string literal
ERROR:Line 79: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 22: Unit ignored due to previous errors.
ERROR:Line 85: Syntax error near "WAIT".
Assuming the asterisk delimited comments aren't part of the VHDL design specification:
You have an extraneous PROCESS and BEGIN:
tb : PROCESS
BEGIN
process (CLOCK)
begin
There's an extra end if:
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
There are more extraneous statements:
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
This should simply be:
end Behavioral;
or
end architecture Behavioral;
And now we find semantic errors:
'CAT' is defined as a scalar std_logic:
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
and used in the component declaration for projetesquema2.
You can't promote it to a std_logic_vector value:
CAT <= "0000";
else
CAT <= CAT + 1;
or add an integer to it like it was declared as an unsigned (the use clause references package numeric_std, and BTW the unisim stuff can be dumped).
The same argument hold true for CRT and CLA. projetesquema appears to translate into English as project plan, there is insufficient information to advise an answerer how to fix these issues.
Perhaps if you made the entity and architecture for projetesquema2 available or told us what it does and what the port names mean?
It seems you've either been thrown in the deep end, missed part of your reading list or haven't been paying attention in class from the errors we see so far.
Stackoverflow may not where you should be going as a first resource for learning VHDL, and the Xilinx tools are somewhat unfriendly for error messages.
I know this it's in English but try this reference for an overview of VHDL.
Right around here you start defining a process inside a process, which isn't legal. Nor does it make much sense.
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
I have a problem with my vhdl code . In active-hdl it works perfectly , but when i tried to implement it on the FPGA board using ise design xilinx i have a problem with one component . The error i found is:
ERROR:Xst:827 - "E:/proiect_final/dispozitiv_impartitor/src/generator_square_wave.vhd" line 16: Signal numar_intermediar<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generator_square_wave is
port(clock,reset :in bit;
controler:std_logic_vector(2 downto 0);
numar:out std_logic_vector(7 downto 0);
data_clock:out bit);
end generator_square_wave ;
architecture descriere of generator_square_wave is
signal reset1:std_logic;
begin
process (clock,reset) -- here it shows me the error
variable numar_intermediar:bit_vector(3 downto 0 ):="0000";
variable numar_intermediar2:std_logic_vector(3 downto 0);
variable bitul:bit;
begin
reset1<=to_stdulogic(reset);
if rising_edge(reset1) then
numar_intermediar:="0001";
numar_intermediar2:=To_StdLogicVector(numar_intermediar);
numar(0)<=numar_intermediar2(0);
numar(1)<=numar_intermediar2(1);
numar(2)<=numar_intermediar2(2);
numar(3)<=numar_intermediar2(3);
numar(4)<='0';
numar(5)<='0';
numar(6)<='0';
numar(7)<='0';
else if( clock'event and clock ='1' and controler="001")then
bitul:=numar_intermediar(0);
numar_intermediar:=numar_intermediar srl 1;
numar_intermediar(3):=bitul;
numar_intermediar2:=To_StdLogicVector(numar_intermediar);
numar(0)<=numar_intermediar2(0);
numar(1)<=numar_intermediar2(1);
numar(2)<=numar_intermediar2(2);
numar(3)<=numar_intermediar2(3);
numar(4)<='0';
numar(5)<='0';
numar(6)<='0';
numar(7)<='0';
if(reset/='1' and controler/="001")then
numar<="00000000";
end if;
end if;
end if;
data_clock<=clock;
end process;
end descriere;
You have a few problems. First, you shouldn't be treating reset as a clock (i.e. using rising_edge()). If it's asynchronous, you should just write:
if reset1 = '1' then
...
The following line also has a problem (not sure if this is strictly illegal, but it's not recommended):
if( clock'event and clock ='1' and controler="001")then
This should be:
if clock'event and clock = '1' then
if controler = "001" then
(with additional end if to match.)
That should at least allow it to synthesize.
You may also want to make the statement reset1<=to_stdulogic(reset) concurrent instead of including it in the process, and there are a couple other possible changes you could make, but they're not as critical (unless I've missed something).
This error has been mindfucking me for long, I don't know what to do. I get the same error in other codes, but this one is a simple one, so maybe it's easier to find out what's the problem.
It's a frequency selector, if the switch (clau) is on, the frequency changes.
library IEEE;
use IEEE.numeric_bit.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity selector_frequencia is
Port ( unHz : in bit ;
centHz : in bit ;
Clock : out bit;
clau: in bit);
end selector_frequencia;
architecture Behavioral of selector_frequencia is
begin
if (clau = "0") then Clock <= unHz;
else Clock <= centHz;
end if;
end Behavioral;
And the error I get is this one:
ERROR:HDLParsers:164 - "C:/Documents and Settings/Administrador/Escritorio/practica_digital/practica_digital/selector_frequencia.vhdl" Line 23. parse error, unexpected IF
Thank you.
I'm not really an expert in VHDL but I believe you should use the if statement inside a process:
architecture Behavioral of selector_frequencia is
begin
fqsel:PROCESS(unHz , centHz , Clock , clau)
BEGIN
if (clau = '0') then
Clock <= unHz;
else
Clock <= centHz;
end if;
END PROCESS fqsel;
end Behavioral;
As Alex pointed out, your if statement needs to be inside a process block. In addition, VHDL is not C...you are not supposed to put parens () around the conditional or it looks like a procedure/function call or a signal range ie: my_bus(7 downto 0) but it's a syntax error because if is a reserved word. Try:
process (clau, unHz, centHz)
begin
if clau = '0' then
Clock <= unHz;
else
Clock <= centHz;
end if;
end process;
Finally, outside of a process, you can just use a conditional signal assignment, which is a short-hand way of implementing the equivalent process and if statements:
Clock <= unHz when clau='0' else centHz;
You are using an assignment statement in your IF clause:
// This is assignment, you are assigning 'clau' to 0 and then checking it in 'if'
if (clau = "0") then Clock <= unHz;
// Try this, note the double '='
if (clau == "0") then Clock <= unHz;
Assignment statements should be within a PROCESS block.
Hope this helps.
i'm coding a 4-bit binary adder with accumulator:
library ieee;
use ieee.std_logic_1164.all;
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout bit;
done:out bit);
end binadder;
architecture binadder of binadder is
signal state: integer range 0 to 3;
signal sum,cin:bit;
begin
sum<= (x(0) xor y(0)) xor cin;
co<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
process
begin
wait until clk='0';
case state is
when 0=>
if(n='1') then
state<=1;
end if;
when 1|2|3=>
if(sh='1') then
x<= sum & x(3 downto 1);
y<= y(0) & y(3 downto 1);
cin<=co;
end if;
if(state=3) then
state<=0;
end if;
end case;
end process;
done<='1' when state=3 else '0';
end binadder;
The output :
-- Compiling architecture binadder of binadder
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
No feasible entries for infix operator
"xor".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
Type error resolving infix expression
"xor" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in left operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Type error resolving infix expression
"or" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
No feasible entries for infix operator
"&".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
Type error resolving infix expression
"&" as type
ieee.std_logic_1164.std_logic_vector.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(39):
VHDL Compiler exiting
I believe i'm not handling std_logic_vector's correctly. Please tell me how? :(
One of the features of VHDL is that very little functionality is provided in the base language itself. Most of it is provided by using packages. The second line of your code is an example of this (use ieee.std_logic_1164.all). This means that you are using all of the std_logic_1164 package. See here for what this package defines.
When you write code, you generally want to store your signals in either std_logic or std_logic_vector. There are two reasons for this. The first is that a std_logic can also represent values other than '0' or '1'. It can also represent 'Z' or 'X' for example. The second is that the simulators (such as modelsim that you are using) are optimised to run faster with std_logic.
As a general convention, it is good practice to always make the inputs and outputs from your entity a std_logic or std_logic_vector.
The specific problem you are having is that you are using the type bit (which is one of the very few types defined in the VHDL standard) with xor.
The simplest solution is to change the co output in your entity to be of type std_logic and to change the declaration for sum and cin to be of type std_logic.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout std_logic;
done:out bit);
end binadder;
signal sum,cin:std_logic;
A further comment is that it is generally bad practice to make your ports inout unless you have a very good reason to do so as this removes some of the strict type checking that is built into the language. The best solution is to create a signal within the entity itself and assign the signal directly to the output.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:out std_logic;
done:out bit);
end binadder;
signal co_int:std_logic;
begin
co_int<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
co <= co_int;
One final comment is that once the value of state is 1, how will it ever become 2 or 3?
Take a look into your logical-physical library mappings.
Check that the physical library actually has the packages dumped.
Make sure you are not using a different version of pre-compiled header with a different version of the simulator.
If nothing works, just make a local copy of ieee, compile the std_logic_1164 packages into it, move to work library and then compile your design. This has to work.