Type error infix expression VHDL - vhdl

I am coding a basic combinational circuit in VHDL, which has an AND gate with two inputs a and b. The output of this "t" is OR'ed with a negated input "c". This output "s" is then NAND with "a" to give the final output "d".
Here's the code.
library ieee;
use ieee.std_logic_1164.all;
entity logicgate is
port(a,b,c: in std_logic;
d: out std_logic);
end logicgate;
architecture arch_logicgate of logicgate is
begin
signal s: std_logic;
signal t: std_logic;
t<= a and b;
s<= (not c) or t;
d<= a nand s;
end arch_logicgate;
Transcript:
-- Compiling architecture arch_logicgate of logicgate
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s".
#
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting
I know I am missing out on the basics. Please help me out.

The first error message:
** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
arises because there are declarations in the execution region.
Put them in the declaration region, before begin
architecture arch_logicgate of logicgate is
signal s: std_logic;
begin
...

Related

two different errors in modelsim when '=' or '<=' used

I'm learning VHDL, and I've been struggling with this simple example below since yesterday.
Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input. The system has three (3) output signals 'LOW' 'MID' and 'HIGH' that generate the following values:
Assume that all signals are of type Std_logic.
The code is like this;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY LMHcounter IS
PORT(clk,reset:in std_logic;
L:out std_logic;
M:out std_logic;
H:out std_logic);
END LMHcounter;
ARCHITECTURE behavior OF UPcounter IS
SIGNAL count:std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk,reset)
BEGIN
if reset='1' then count<="0000";
elsif (rising_edge(clk))then
if count<="1001" then
count<="0000";
else count<=count+"0001";
end if;
end if;
END PROCESS;
L<='1' when count<="0101";
else '0';
M<='1' when count="0110";
else '0';
H<='1' when count>="0111";
else '0';
END behavior;
If I use L='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): near "=": (vcom-1576) expecting == or '+' or '-' or '&'.
If I use L<='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): Illegal target for signal assignment.
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1136) Unknown identifier "L".
Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I can't use ':=' as apparently modelsim does not support
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1441) CONDITIONAL VARIABLE ASSIGNMENT is not defined for this version of the language.
** Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I'm sure it's trivial, but I can't seem to find an answer anywhere. And also can someone explain please what is happening in the background if I use '=' or '<='?
Thanks
There are quite a few errors i found,
Firstly, you are trying to describe an architecture for a different entity other than the one you declared. I guess that should be ARCHITECTURE behavior OF LMHcounterIS instead of ARCHITECTURE behavior OF UPcounter IS
The syntax for the conditional signal assignment is wrong, you should use it as
signal <= [expression when condition else ...] expression;. In your code that should be L<='1' when count<="0101" else '0';
M<='1' when count="0110" else '0';
H<='1' when count>="0111" else '0';

vhdl error code 10500 for keywords already present

This code is for a PRBS (pseudo-random binary sequence) receiver. it is supposed to take three values and simulate a PRBS generator and check the obtained vales with the values generated.
But the code is showing errors for keywords like begin which are already present
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity receiver is
port(
inp : in std_logic;
clock : in std_logic;
count : out std_logic_vector(4 downto 0);
check : out std_logic);
end receiver;
architecture rec of receiver is
signal P : std_logic_vector(2 downto 0);
signal O : std_logic_vector(2 downto 0);
process (clock)
variable cnt : integer range 0 to 3;
begin
if clock'event and clock='1' then
P <= inp & P(2 downto 1);
cnt<=cnt+1;
end if;
if (cnt = 3) then
O<=P;
elseif (cnt >3)
O <= inp & O(2 downto 1);
end if;
if((O(2) xor O(0)) = P(0))
check <= '0';
else
check <= '1';
count <= count +1;
end if;
end process;
end rec;
Error (10500): VHDL syntax error at receiver.vhd(18) near text "process"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "and"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(24) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(25) near text "then"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(28) near text "O"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(29) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(31) near text "check"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
The structure of your entity needs to look like this:
entity receiver is
port (
-- Your ports
);
end receiver;
architecture rec of receiver is
-- Declarations here
begin -- ** Your code is missing this part
process (clock)
begin
-- your process
end process;
end rec;
As mentioned in the comments, always start with the first error you see; understand and solve that one first, and many later errors will normally go away as a result.
You have declared cnt as a variable, and then are trying to increment it using cnt <= cnt + 1;, but variables assignment should use := not <=.
The next error is your use of elseif; this is not a real keyword, and it looks like you wanted to use elsif. This line is also missing a then.
You then have a line if((O(2) xor O(0)) = P(0)), which is again missing a then.
Lastly, you are trying to directly increment count which is an out port. This is not possible, since you are trying to read an output in order to add one to it; there are a few ways to resolve this, but personally I would create an intermediate signal (e.g. count_s), which you use in your process, then assign your output to this signal with count <= count_s, somewhere outside the process.
With all these issues resolved, your code at least compiles.
As a side note, it would help you to have better vertical alignment of your code; your end process should vertically align with its opening process, and so on.

VHDL Compile error

trying to figure out why this VHDL code keeps giving back compile errors. I cannot get it to like the code no matter what I try.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LabM5 is
port(
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC
);
end LabM5;
architecture behv of LabM5 is
begin
process(X, Y)
begin
if (X='1' and Y='1')then Z='1'; end if;
end process;
end behv;
errors are:
Error: COMP96_0015: Lab M5.vhd : (16, 30): ';' expected.
Error: COMP96_0019: Lab M5.vhd : (16, 30): Keyword "end" expected.
Error: COMP96_0019: Lab M5.vhd : (16, 40): Keyword "process" expected.
Error: COMP96_0015: Lab M5.vhd : (17, 7): ';' expected.
Error: COMP96_0016: Lab M5.vhd : (17, 14): Design unit declaration expected.
line 16 is the if statement and line 17 is the end process
Port and signal assign is made with <= in VHDL, so change the assign in if to Z<='1'.
Btw; when will Z get any other value than '1' ?
You'll make that mistake many times, since the equal operators are very different than other languages.
Variable: Use := to assign a value.
Signal: Use <= to assign a value.
Starting Value: Use := to assign the starting value, even if you're defining a signal.

VHDL When statement with multiple conditions

I am new to VHDL. I am trying to set a signals value based on the state of multiple conditions. It is outside of a process block. Is what I am trying to do even possible? If so, what am I doing wrong?
This is what I have so far:
signal1<= my_data
WHEN ( bit_cond_true
AND (my_array /= X"00000")
AND (my_array = another_array))
ELSE
other_data;
This is what happens when I try to compile it in ModelSim:
** Error: file.VHD(62): No feasible entries for infix operator "and".
** Error: file.VHD(62): Bad expression in left operand of infix expression "and".
** Error: file.VHD(62): Type error resolving infix expression "and" as type std.standard.boolean.
** Error: file.VHD(67): No feasible entries for infix operator "and".
** Error: file.VHD(66): Bad expression in left operand of infix expression "and".
** Error: file.VHD(67): Type error resolving infix expression "and" as type std.standard.boolean.
** Error: file.VHD(100): VHDL Compiler exiting
First, what you are trying to do is indeed possible, and is called a "conditional signal assignment statement" in VHDL terms.
You have not provided the declarations for the signals used in the expression, but I will assume that they are all std_logic or std_logic_vector, thus:
signal signal1 : std_logic; -- Result
signal my_data : std_logic; -- Value if TRUE condition
signal other_data : std_logic; -- Value if FALSE condition
signal bit_cond_true : std_logic; -- Condition part
signal my_array : std_logic_vector(19 downto 0); -- --||--
signal another_array : std_logic_vector(19 downto 0); -- --||--
So, VHDL is a strong typed language, and the condition you have given for when can't resolve because bit_cond_true is a std_logic, and (my_array /= X"00000") resolves to a boolean. Therefore you get the ModelSim error No feasible entries for infix operator "and". since ModelSim tries to resolve an expression with {std_logic} and {boolean}, but it has no definition of the and operator with the combinations of arguments.
There are different possibilities for converting bit_cond_true to a boolean, and this goes with both VHDL-2002 and VHDL-2008:
signal1 <= my_data when ((bit_cond_true = '1') and
(my_array /= X"00000") and
(my_array = another_array)) else
other_data;
In VHDL-2008 only, you can also use the ?? operator to convert a std_logic value of '1' or 'H' to TRUE, and other values to FALSE. The code then looks:
signal1 <= my_data when ((?? bit_cond_true) and
(my_array /= X"00000") and
(my_array = another_array)) else
other_data;
To get more into the VHDL language, I would recommend that you dive into one of the books listen under "Further reading" in Wikipedia VHDL

VHDL - Problem with std_logic_vector

i'm coding a 4-bit binary adder with accumulator:
library ieee;
use ieee.std_logic_1164.all;
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout bit;
done:out bit);
end binadder;
architecture binadder of binadder is
signal state: integer range 0 to 3;
signal sum,cin:bit;
begin
sum<= (x(0) xor y(0)) xor cin;
co<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
process
begin
wait until clk='0';
case state is
when 0=>
if(n='1') then
state<=1;
end if;
when 1|2|3=>
if(sh='1') then
x<= sum & x(3 downto 1);
y<= y(0) & y(3 downto 1);
cin<=co;
end if;
if(state=3) then
state<=0;
end if;
end case;
end process;
done<='1' when state=3 else '0';
end binadder;
The output :
-- Compiling architecture binadder of binadder
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
No feasible entries for infix operator
"xor".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):
Type error resolving infix expression
"xor" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
No feasible entries for infix operator
"and".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in left operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Bad expression in right operand of
infix expression "or".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):
Type error resolving infix expression
"or" as type std.standard.bit.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
No feasible entries for infix operator
"&".
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):
Type error resolving infix expression
"&" as type
ieee.std_logic_1164.std_logic_vector.
** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(39):
VHDL Compiler exiting
I believe i'm not handling std_logic_vector's correctly. Please tell me how? :(
One of the features of VHDL is that very little functionality is provided in the base language itself. Most of it is provided by using packages. The second line of your code is an example of this (use ieee.std_logic_1164.all). This means that you are using all of the std_logic_1164 package. See here for what this package defines.
When you write code, you generally want to store your signals in either std_logic or std_logic_vector. There are two reasons for this. The first is that a std_logic can also represent values other than '0' or '1'. It can also represent 'Z' or 'X' for example. The second is that the simulators (such as modelsim that you are using) are optimised to run faster with std_logic.
As a general convention, it is good practice to always make the inputs and outputs from your entity a std_logic or std_logic_vector.
The specific problem you are having is that you are using the type bit (which is one of the very few types defined in the VHDL standard) with xor.
The simplest solution is to change the co output in your entity to be of type std_logic and to change the declaration for sum and cin to be of type std_logic.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:inout std_logic;
done:out bit);
end binadder;
signal sum,cin:std_logic;
A further comment is that it is generally bad practice to make your ports inout unless you have a very good reason to do so as this removes some of the strict type checking that is built into the language. The best solution is to create a signal within the entity itself and assign the signal directly to the output.
entity binadder is
port(n,clk,sh:in bit;
x,y:inout std_logic_vector(3 downto 0);
co:out std_logic;
done:out bit);
end binadder;
signal co_int:std_logic;
begin
co_int<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
co <= co_int;
One final comment is that once the value of state is 1, how will it ever become 2 or 3?
Take a look into your logical-physical library mappings.
Check that the physical library actually has the packages dumped.
Make sure you are not using a different version of pre-compiled header with a different version of the simulator.
If nothing works, just make a local copy of ieee, compile the std_logic_1164 packages into it, move to work library and then compile your design. This has to work.

Resources