vhdl error code 10500 for keywords already present - vhdl

Question

This code is for a PRBS (pseudo-random binary sequence) receiver. it is supposed to take three values and simulate a PRBS generator and check the obtained vales with the values generated.
But the code is showing errors for keywords like begin which are already present
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity receiver is
port(
inp : in std_logic;
clock : in std_logic;
count : out std_logic_vector(4 downto 0);
check : out std_logic);
end receiver;
architecture rec of receiver is
signal P : std_logic_vector(2 downto 0);
signal O : std_logic_vector(2 downto 0);
process (clock)
variable cnt : integer range 0 to 3;
begin
if clock'event and clock='1' then
P <= inp & P(2 downto 1);
cnt<=cnt+1;
end if;
if (cnt = 3) then
O<=P;
elseif (cnt >3)
O <= inp & O(2 downto 1);
end if;
if((O(2) xor O(0)) = P(0))
check <= '0';
else
check <= '1';
count <= count +1;
end if;
end process;
end rec;
Error (10500): VHDL syntax error at receiver.vhd(18) near text "process"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "and"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(24) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(25) near text "then"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(28) near text "O"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(29) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(31) near text "check"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Answer 1

The structure of your entity needs to look like this:
entity receiver is
port (
-- Your ports
);
end receiver;
architecture rec of receiver is
-- Declarations here
begin -- ** Your code is missing this part
process (clock)
begin
-- your process
end process;
end rec;
As mentioned in the comments, always start with the first error you see; understand and solve that one first, and many later errors will normally go away as a result.
You have declared cnt as a variable, and then are trying to increment it using cnt <= cnt + 1;, but variables assignment should use := not <=.
The next error is your use of elseif; this is not a real keyword, and it looks like you wanted to use elsif. This line is also missing a then.
You then have a line if((O(2) xor O(0)) = P(0)), which is again missing a then.
Lastly, you are trying to directly increment count which is an out port. This is not possible, since you are trying to read an output in order to add one to it; there are a few ways to resolve this, but personally I would create an intermediate signal (e.g. count_s), which you use in your process, then assign your output to this signal with count <= count_s, somewhere outside the process.
With all these issues resolved, your code at least compiles.
As a side note, it would help you to have better vertical alignment of your code; your end process should vertically align with its opening process, and so on.