Need help VHDL in Xilinx - vhdl

So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock signal. The code I developed was something like these (it was based on a schematic so the entity and architecture is supposed to remain untouched I think):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY projetesquema2_projetesquema2_sch_tb IS
END projetesquema2_projetesquema2_sch_tb;
ARCHITECTURE behavioral OF projetesquema2_projetesquema2_sch_tb IS
COMPONENT projetesquema2
PORT( CLOCK : IN STD_LOGIC;
ACL : IN STD_LOGIC;
CAT : OUT STD_LOGIC;
CRT : OUT STD_LOGIC;
CLT : OUT STD_LOGIC;
ACA : IN STD_LOGIC);
END COMPONENT;
SIGNAL CLOCK : STD_LOGIC;
SIGNAL ACL : STD_LOGIC;
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
BEGIN
UUT: projetesquema2 PORT MAP(
CLOCK => CLOCK,
ACL => ACL,
CAT => CAT,
CRT => CRT,
CLT => CLT,
ACA => ACA
);
*** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACA='0') then
CAT <= "0000";
else
CAT <= CAT + 1;
end if;
end if;
end process;
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACL='0') then
CLT <= "0000";
else
CLT <= CLT + 1;
end if;
end if;
end process;
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
*** End Test Bench - User Defined Section ***
END;
This gives me some errors that I don't know how to fix, hope somebody can actually help me.
Errors are:
ERROR:Line 54: Syntax error near "process".
ERROR:Line 55: Syntax error near "begin".
ERROR:Line 58: Type std_logic does not match with a string literal
ERROR:Line 60: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 68: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 70: Syntax error near "if".
ERROR:Line 77: Type std_logic does not match with a string literal
ERROR:Line 79: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 22: Unit ignored due to previous errors.
ERROR:Line 85: Syntax error near "WAIT".

Assuming the asterisk delimited comments aren't part of the VHDL design specification:
You have an extraneous PROCESS and BEGIN:
tb : PROCESS
BEGIN
process (CLOCK)
begin
There's an extra end if:
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
There are more extraneous statements:
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
This should simply be:
end Behavioral;
or
end architecture Behavioral;
And now we find semantic errors:
'CAT' is defined as a scalar std_logic:
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
and used in the component declaration for projetesquema2.
You can't promote it to a std_logic_vector value:
CAT <= "0000";
else
CAT <= CAT + 1;
or add an integer to it like it was declared as an unsigned (the use clause references package numeric_std, and BTW the unisim stuff can be dumped).
The same argument hold true for CRT and CLA. projetesquema appears to translate into English as project plan, there is insufficient information to advise an answerer how to fix these issues.
Perhaps if you made the entity and architecture for projetesquema2 available or told us what it does and what the port names mean?
It seems you've either been thrown in the deep end, missed part of your reading list or haven't been paying attention in class from the errors we see so far.
Stackoverflow may not where you should be going as a first resource for learning VHDL, and the Xilinx tools are somewhat unfriendly for error messages.
I know this it's in English but try this reference for an overview of VHDL.

Right around here you start defining a process inside a process, which isn't legal. Nor does it make much sense.
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then

Related

VHDL enumerator relational operators

I'm currently programming a system in VHDL, and I'm using an enumerator from another package called vnir, which is defined as such:
package vnir is
type row_type_t is (ROW_NONE, ROW_NIR, ROW_BLUE, ROW_RED);
end package vnir;
I've defined my architecture as such
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
The internal signal vnir_row_ready_i can be assigned to no problem, however the relational operator doesn't seem to work as ModelSim throws this error when I try to compile:
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): (vcom-1581) No feasible entries for infix operator '/='.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): Type error resolving infix expression "/=" as type std.STANDARD.BOOLEAN.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(28): VHDL Compiler exiting
My coworker helped me figure out how to make it work! I think that the /= operator is created in the vnir scope, but not ported over to the entity I'm working on. By writing :use work.vnir."/="; at the beginning of the file it compiles, so the full entity looks like so:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vnir;
use work.vnir."/=";
entity imaging_buffer is
port(
clock : in std_logic;
reset_n : in std_logic;
vnir_row_ready : in vnir.row_type_t
);
end entity imaging_buffer;
architecture rtl of imaging_buffer is
signal vnir_row_ready_i : vnir.row_type_t;
begin
vnir_pipeline : process (reset_n, clock) is
begin
if (reset_n = '0') then
vnir_row_ready_i <= vnir.ROW_NONE;
elsif rising_edge(clock) then
if (vnir_row_ready /= vnir.ROW_NONE) then
--do stuff
end if;
end if;
end process vnir_pipeline;
end architecture;
Alternatively it did work by including use work.vnir.all; and taking out the vnir. before the types, but that wasn't possible with the project I'm working one

Test bench file for integer types

I'm trying to simulate the following VHDL module in XIlinx ISE 14.7, but the generated VHDL test bench file assumes that all input and output ports are of type std_logic and std_logic_vector.
package newtype is
type row_t is array(0 to 2) of integer;
end newtype;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.newtype.all;
entity mymodule is
port (indata : in row_t;
sum : out integer);
end mymodule;
architecture Behavioral of mymodule is
begin
process (indata)
begin
sum <= indata(0) + indata(1) + indata(2);
end process;
end Behavioral;
I modified the generated code replacing std_logic_vector with my types, but this time it gives me syntax errors.
Could you please tell me what is the right way write a text bench file when you work with integer types?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.newtype.all;
ENTITY mymodule_test IS
END mymodule_test;
ARCHITECTURE behavior OF mymodule_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mymodule
PORT(
indata : IN row_t;
sum : OUT integer
);
END COMPONENT;
--Inputs
signal indata : row_t := (0,0,0);
--Outputs
signal sum : integer;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mymodule PORT MAP (
indata => indata,
sum => sum
);
-- Clock process definitions
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
END;
You haven't posted the syntax errors you encountered. But, if I create a new project in Xilix ISE 14.7 and just add the above code, I get these syntax errors:
ERROR:HDLCompiler:806 -
"mymodule_test.vhdl"
Line 28: Syntax error near "<". ERROR:HDLCompiler:806 -
"mymodule_test.vhdl"
Line 39: Syntax error near "<". ERROR:HDLCompiler:806 -
"mymodule_test.vhdl"
Line 41: Syntax error near "<". ERROR:HDLCompiler:806 -
"mymodule_test.vhdl"
Line 54: Syntax error near "<".
All these lines contain the indentifier or prefix <clock> which is a template parameter of Xilinx's testbench generator. If this, generator detects a clock within the design you have selected in the wizard (here mymodule), then <clock> is replaced by the actual name of the clock signal. The testbench generator didn't found a clock signal within your design, so it just inserted the plain template code. These syntax errors are not related to the usage of the type integer within the testbench.
Your design does not depend on a clock signal, so you can safely remove all the testbench code associated with the clock signal:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.newtype.all;
ENTITY mymodule_test IS
END mymodule_test;
ARCHITECTURE behavior OF mymodule_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mymodule
PORT(
indata : IN row_t;
sum : OUT integer
);
END COMPONENT;
--Inputs
signal indata : row_t := (0,0,0);
--Outputs
signal sum : integer;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mymodule PORT MAP (
indata => indata,
sum => sum
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;

VHDL Program counter using signals and previously made components?

I am currently in the middle of a project where I am attempting to design a single cycle cpu. I am doing this without any pipe-lining, since that would greatly add to the complexity of the design. I am simply taking baby steps as I learn this. I find myself stuck at this portion where I am simply attempting to code a Program Counter(PC) using previously made components.
The model of my design looks like this picture here. Sorry, no idea why it came out dark, but if you click on it it shows correctly. The PC and theMUX are both 32 bit components, so I assume the adder is as well.
Here is the code I have been given, my implementation begins at the begin statement on line 41.
Pay no attention to it for now, its just a bunch of random gibberish I was attempting.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity pc_update is
port( clk: in std_logic; -- clock
incH_ldL: in std_logic; -- increment PC = PC + 4 when high,
-- load PCInput when low
PCInput: in std_logic_vector(31 downto 0); -- external input for PC
InstrAddr: out std_logic_vector(31 downto 0) ); -- instruction address
end entity pc_update;
----------------------------------------------------
architecture pc_update_arch of pc_update is
component register32 is
port( clr: in std_logic; -- async. clear
clk: in std_logic; -- clock
ld: in std_logic; -- load
D: in std_logic_vector(31 downto 0); -- data input
Q: out std_logic_vector(31 downto 0) ); -- data output
end component register32;
component mux2to1_32 is
port( sel: in std_logic; -- selection bit input
X0: in std_logic_vector(31 downto 0); -- first input
X1: in std_logic_vector(31 downto 0); -- second input
Y: out std_logic_vector(31 downto 0)); -- output
end component mux2to1_32;
signal PC_current: std_logic_vector(31 downto 0); -- the current state of PC reg
signal PC_add_4: std_logic_vector(31 downto 0); -- output from the adder
signal PC_next: std_logic_vector(31 downto 0); -- output from the MUX
begin
PC: register32 Port Map(
clk, Q, clr, D);
MUX: mux2to1_32 Port Map(
X0,sel,X1,Y);
process (incH_ldL)
begin
wait until (clk = '1');
if incH_1dL = '0' then
InstrAddr <= X0;
else InstrAddr <= X1;
end if;
end process;
end architecture pc_update_arch;
I am fairly new to this so I have only a faint idea of how signals work, and no idea how I am supposed to implement the components into the design. I am also confused that I wasnt asked to build the adder ahead of time. Is it now necessary to use it as a component im guessing?
Anyhow, I have attempted different things that stumbled upon searching, such as the port mapping you see. But I always get some sort of error, currently the error im receiving is that objects Q, clr, and D are used but not declared. How do I declare them?
If I get rid of those statements, the error simply repeats for objects X0, X1, and Y.
Any help in the right direction would be greatly appreciated. Thanks guys!
Also, just in case you need them,
The register
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity register32 is port(
clr: in std_logic; -- async. clear
clk: in std_logic; -- clock
ld: in std_logic; -- load
D: in std_logic_vector(31 downto 0); -- data input
Q: out std_logic_vector(31 downto 0) ); -- data output
end entity register32;
----------------------------------------------------
architecture register32_arch of register32 is
begin
process(clk, clr)
begin
if clr = '1' then
q <= x"00000000";
elsif rising_edge(clk) then
if ld = '1' then
q <= d;
end if;
end if;
end process;
END register32_arch;
and the MUX
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity mux2to1_32 is
port( sel: in std_logic; -- selection bit input
X0: in std_logic_vector(31 downto 0); -- first input
X1: in std_logic_vector(31 downto 0); -- second input
Y: out std_logic_vector(31 downto 0)); -- output
end entity mux2to1_32;
----------------------------------------------------
architecture mux2to1_32_arch of mux2to1_32 is
begin
Y <= X1 when (SEL = '1') else X0;
end architecture mux2to1_32_arch;
EDIT
Ok, NO idea if I did this correctly, but I rewrote the portmaps. I was having errors of port names (sel, clk, X0, X1..etc) being "used but not initialized. So that is why clr, clk and ld have initial values. Once again, no idea if that is correct, but it made the errors go away. I also realized I never added the register32 and mux2to1_32 VHDL files to my project, and after doing so got rid of the other errors I was having.
So as stands, the code compiles, I have included in the project a VWF simulation file for testing, but I KNOW the results are gonna be incorrect.
I dont know everything that is wrong yet, but I know I need to do something with PC_add_4. THis value needs to basically be (PC_current + 4), but Im not sure how to do this.
Here is the updated portion of code(everything else is the same)
PC: register32 Port Map(
clr => '0',
clk => '0',
ld => '1',
Q => PC_current,
D => PC_next
);
MUX: mux2to1_32 Port Map(
sel => incH_ldL,
X0 => PCInput ,
X1 => PC_add_4,
Y => PC_next
);
process (incH_ldL)
begin
if (rising_edge(clk)) then
if incH_ldL = '0' then
InstrAddr <= PC_current;
else InstrAddr <= PC_add_4;
end if;
end if;
end process;
And, in case they help, my list of errors..im guessing the pin related errors are because I dont have any hardware assignments made yet.
Warning (10541): VHDL Signal Declaration warning at pc_update.vhd(38): used implicit default value for signal "PC_add_4" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10492): VHDL Process Statement warning at pc_update.vhd(61): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Output pins are stuck at VCC or GND
Warning: Design contains 34 input pin(s) that do not drive logic
Warning: Found 32 output pins without output pin load capacitance assignment
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode
Warning: No paths found for timing analysis
Critical Warning: No exact pin location assignment(s) for 66 pins of 66 total pins
SECOND EDIT
So yeah I fixed up my code by adding
PC_add_4 <= (PC_current + 4 );
after the port mappings, and adding "clk" to the process sensitivity list.
However my waveforms in my simulation are still wrong I believe, as shown here.
It appears to be treating incH_lDL as a clear signal, rather than simply passing PCInput to InstrAddr. This is most likely due to my setting of it to a default '0' in the port map. I did this earlier because it was giving me "used but not declared" errors. Ill try messing with it and post my findings.
Third EDIT
I have edited my code as such:
process (incH_ldL, clk)
begin
if rising_edge(clk) then
if (incH_ldL = '0') then
InstrAddr <= PCInput ;
else InstrAddr <= PC_add_4;
end if;
end if;
end process;
My simulation now shows that when incH_lDL = 0, PCInput is loaded into InstrAddr, however, when incH_lDL = 1, it simply loads the value '4', and doesnt increment at the start of every clock cycle like its supposed to...I need to make use of PC_current, but I am not sure how....sicne you cant assign one signal to another like "PC_current <= PCInput". I will try some more things,in the mean time, any pointers would be greatly appreciated.
FOURTH EDIT
THanks to anyone still reading this, and bearing through all the reading.
I have attempted to use PC_next and PC_current in my implementation, but have run into "multiple constant drivers for net "PC_next" errors.
MY process code:
process (incH_ldL, clk, PC_next, PC_current)
begin
if rising_edge(clk) then
if (incH_ldL = '0') then
PC_next <= PCInput;
else PC_next <= PC_add_4;
end if;
end if;
InstrAddr <= PC_current;
end process;
I am aware that this error comes when these assignments are made within loops? I am truly at a loss here at what to try next.
Your port maps in the first code need to be ported to signals. You are placing the port names of the components in the port map, which is incorrect. What you would like to do is create signals that can connect those components, and place them in the port map fields instead (to match the connections in your image).

Vhdl ERROR that I don't understand

I have a problem with my vhdl code . In active-hdl it works perfectly , but when i tried to implement it on the FPGA board using ise design xilinx i have a problem with one component . The error i found is:
ERROR:Xst:827 - "E:/proiect_final/dispozitiv_impartitor/src/generator_square_wave.vhd" line 16: Signal numar_intermediar<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generator_square_wave is
port(clock,reset :in bit;
controler:std_logic_vector(2 downto 0);
numar:out std_logic_vector(7 downto 0);
data_clock:out bit);
end generator_square_wave ;
architecture descriere of generator_square_wave is
signal reset1:std_logic;
begin
process (clock,reset) -- here it shows me the error
variable numar_intermediar:bit_vector(3 downto 0 ):="0000";
variable numar_intermediar2:std_logic_vector(3 downto 0);
variable bitul:bit;
begin
reset1<=to_stdulogic(reset);
if rising_edge(reset1) then
numar_intermediar:="0001";
numar_intermediar2:=To_StdLogicVector(numar_intermediar);
numar(0)<=numar_intermediar2(0);
numar(1)<=numar_intermediar2(1);
numar(2)<=numar_intermediar2(2);
numar(3)<=numar_intermediar2(3);
numar(4)<='0';
numar(5)<='0';
numar(6)<='0';
numar(7)<='0';
else if( clock'event and clock ='1' and controler="001")then
bitul:=numar_intermediar(0);
numar_intermediar:=numar_intermediar srl 1;
numar_intermediar(3):=bitul;
numar_intermediar2:=To_StdLogicVector(numar_intermediar);
numar(0)<=numar_intermediar2(0);
numar(1)<=numar_intermediar2(1);
numar(2)<=numar_intermediar2(2);
numar(3)<=numar_intermediar2(3);
numar(4)<='0';
numar(5)<='0';
numar(6)<='0';
numar(7)<='0';
if(reset/='1' and controler/="001")then
numar<="00000000";
end if;
end if;
end if;
data_clock<=clock;
end process;
end descriere;
You have a few problems. First, you shouldn't be treating reset as a clock (i.e. using rising_edge()). If it's asynchronous, you should just write:
if reset1 = '1' then
...
The following line also has a problem (not sure if this is strictly illegal, but it's not recommended):
if( clock'event and clock ='1' and controler="001")then
This should be:
if clock'event and clock = '1' then
if controler = "001" then
(with additional end if to match.)
That should at least allow it to synthesize.
You may also want to make the statement reset1<=to_stdulogic(reset) concurrent instead of including it in the process, and there are a couple other possible changes you could make, but they're not as critical (unless I've missed something).

"EOF" : syntax error at line 2

I'm trying to write a simple vhdl code. When I run this code in quartus 2 there is no problem. However, when I run on modelsim, there is an error at line 2, that is error at "use ieee.std_logic_all.1164;" . I have no clue since I'm new to vhdl. By the way, i'm using Modelsim Starter edition 6.5e
library ieee;
use ieee.std_logic_all.1164;
entity tb is
end tb;
architecture behaviour of tb is
component ORG is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic;
);
signal ina, inb, outc : std_logic;
constant period : time := 100ns;
signal done : boolean := false;
begin
process
begin
ina = '0';
inb = '0';
wait for period;
ina = '1';
inb = '0'
wait for period;
done <= true;
wait;
end process;
end behaviour;
You have a number of problems in your code that will cause syntax errors.
As #rene pointed out, the library name is std_logic_1164 - you have "1164" and "all" reversed (the capitalization of IEEE isn't significant).
There should not be a semicolon at the end of the c port line
You should include an end component; statement after the port declaration (that is, after the closing parenthesis and semicolon)
The equals signs in the process should be <=
Finally, there should be a space between 100 and ns

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