I am trying to compile a test bench that use alias. This testbench is compiled in VHDL2008 but
alias reg_test is << signal dut.i_dut_int.extra_signal : std_logic >>;
returns:
* Error: near "alias": syntax error
where ever i put this line.
What is the problem?
Related
I'm learning VHDL, and I've been struggling with this simple example below since yesterday.
Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input. The system has three (3) output signals 'LOW' 'MID' and 'HIGH' that generate the following values:
Assume that all signals are of type Std_logic.
The code is like this;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY LMHcounter IS
PORT(clk,reset:in std_logic;
L:out std_logic;
M:out std_logic;
H:out std_logic);
END LMHcounter;
ARCHITECTURE behavior OF UPcounter IS
SIGNAL count:std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk,reset)
BEGIN
if reset='1' then count<="0000";
elsif (rising_edge(clk))then
if count<="1001" then
count<="0000";
else count<=count+"0001";
end if;
end if;
END PROCESS;
L<='1' when count<="0101";
else '0';
M<='1' when count="0110";
else '0';
H<='1' when count>="0111";
else '0';
END behavior;
If I use L='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): near "=": (vcom-1576) expecting == or '+' or '-' or '&'.
If I use L<='1' at the end I get;
Error: C:/DL_Project/LMH Counter.vhd(29): Illegal target for signal assignment.
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1136) Unknown identifier "L".
Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I can't use ':=' as apparently modelsim does not support
Error: C:/DL_Project/LMH Counter.vhd(29): (vcom-1441) CONDITIONAL VARIABLE ASSIGNMENT is not defined for this version of the language.
** Error: C:/DL_Project/LMH Counter.vhd(30): near "else": (vcom-1576) expecting END.
I'm sure it's trivial, but I can't seem to find an answer anywhere. And also can someone explain please what is happening in the background if I use '=' or '<='?
Thanks
There are quite a few errors i found,
Firstly, you are trying to describe an architecture for a different entity other than the one you declared. I guess that should be ARCHITECTURE behavior OF LMHcounterIS instead of ARCHITECTURE behavior OF UPcounter IS
The syntax for the conditional signal assignment is wrong, you should use it as
signal <= [expression when condition else ...] expression;. In your code that should be L<='1' when count<="0101" else '0';
M<='1' when count="0110" else '0';
H<='1' when count>="0111" else '0';
This code is for a PRBS (pseudo-random binary sequence) receiver. it is supposed to take three values and simulate a PRBS generator and check the obtained vales with the values generated.
But the code is showing errors for keywords like begin which are already present
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity receiver is
port(
inp : in std_logic;
clock : in std_logic;
count : out std_logic_vector(4 downto 0);
check : out std_logic);
end receiver;
architecture rec of receiver is
signal P : std_logic_vector(2 downto 0);
signal O : std_logic_vector(2 downto 0);
process (clock)
variable cnt : integer range 0 to 3;
begin
if clock'event and clock='1' then
P <= inp & P(2 downto 1);
cnt<=cnt+1;
end if;
if (cnt = 3) then
O<=P;
elseif (cnt >3)
O <= inp & O(2 downto 1);
end if;
if((O(2) xor O(0)) = P(0))
check <= '0';
else
check <= '1';
count <= count +1;
end if;
end process;
end rec;
Error (10500): VHDL syntax error at receiver.vhd(18) near text "process"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(21) near text "and"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(24) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(25) near text "then"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(28) near text "O"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at receiver.vhd(29) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error (10500): VHDL syntax error at receiver.vhd(31) near text "check"; expecting "<="
Error (10500): VHDL syntax error at receiver.vhd(32) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at receiver.vhd(35) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
The structure of your entity needs to look like this:
entity receiver is
port (
-- Your ports
);
end receiver;
architecture rec of receiver is
-- Declarations here
begin -- ** Your code is missing this part
process (clock)
begin
-- your process
end process;
end rec;
As mentioned in the comments, always start with the first error you see; understand and solve that one first, and many later errors will normally go away as a result.
You have declared cnt as a variable, and then are trying to increment it using cnt <= cnt + 1;, but variables assignment should use := not <=.
The next error is your use of elseif; this is not a real keyword, and it looks like you wanted to use elsif. This line is also missing a then.
You then have a line if((O(2) xor O(0)) = P(0)), which is again missing a then.
Lastly, you are trying to directly increment count which is an out port. This is not possible, since you are trying to read an output in order to add one to it; there are a few ways to resolve this, but personally I would create an intermediate signal (e.g. count_s), which you use in your process, then assign your output to this signal with count <= count_s, somewhere outside the process.
With all these issues resolved, your code at least compiles.
As a side note, it would help you to have better vertical alignment of your code; your end process should vertically align with its opening process, and so on.
Can anyone see what is wrong with my code?
I get a error on the comment line. Saying syntax error near text. I tried to change from both binary to hex numbers, but keep getting the same error.
Were the errors are is comment selected.
This are the errors:
Error (10500): VHDL syntax error at MAL.vhd(26) near text
Error (10500): VHDL syntax error at MAL.vhd(26) near text ""; expecting "then"
Error (10500): VHDL syntax error at MAL.vhd(26) near text
Error (10500): VHDL syntax error at MAL.vhd(26) near text ¬
Error (10500): VHDL syntax error at MAL.vhd(29) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at MAL.vhd(31) near text "if"; expecting "process"
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY MAL IS
PORT (
clk_50 : IN std_logic;
pulse_out : OUT std_logic
);
END MAL;
ARCHITECTURE behave OF MAL IS
SIGNAL pulse : std_logic;
SIGNAL counter : std_logic_vector(15 DOWNTO 0);
BEGIN
PROCESS (clk_50) IS
BEGIN
pulse <= '0';
-- if counter = x"C34F" then
-- counter <= (others => '0');
pulse <= '1';
-- else
counter <= counter + 1;
END IF;
END PROCESS;
--output
pulse_out <= pulse;
END ARCHITECTURE behave;
You have some illegal character in there. Remove line 27 and re-write it and you should be ok.
trying to figure out why this VHDL code keeps giving back compile errors. I cannot get it to like the code no matter what I try.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LabM5 is
port(
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC
);
end LabM5;
architecture behv of LabM5 is
begin
process(X, Y)
begin
if (X='1' and Y='1')then Z='1'; end if;
end process;
end behv;
errors are:
Error: COMP96_0015: Lab M5.vhd : (16, 30): ';' expected.
Error: COMP96_0019: Lab M5.vhd : (16, 30): Keyword "end" expected.
Error: COMP96_0019: Lab M5.vhd : (16, 40): Keyword "process" expected.
Error: COMP96_0015: Lab M5.vhd : (17, 7): ';' expected.
Error: COMP96_0016: Lab M5.vhd : (17, 14): Design unit declaration expected.
line 16 is the if statement and line 17 is the end process
Port and signal assign is made with <= in VHDL, so change the assign in if to Z<='1'.
Btw; when will Z get any other value than '1' ?
You'll make that mistake many times, since the equal operators are very different than other languages.
Variable: Use := to assign a value.
Signal: Use <= to assign a value.
Starting Value: Use := to assign the starting value, even if you're defining a signal.
I am coding a basic combinational circuit in VHDL, which has an AND gate with two inputs a and b. The output of this "t" is OR'ed with a negated input "c". This output "s" is then NAND with "a" to give the final output "d".
Here's the code.
library ieee;
use ieee.std_logic_1164.all;
entity logicgate is
port(a,b,c: in std_logic;
d: out std_logic);
end logicgate;
architecture arch_logicgate of logicgate is
begin
signal s: std_logic;
signal t: std_logic;
t<= a and b;
s<= (not c) or t;
d<= a nand s;
end arch_logicgate;
Transcript:
-- Compiling architecture arch_logicgate of logicgate
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s".
#
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting
I know I am missing out on the basics. Please help me out.
The first error message:
** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
arises because there are declarations in the execution region.
Put them in the declaration region, before begin
architecture arch_logicgate of logicgate is
signal s: std_logic;
begin
...