I want to make a simple makefile for a C project that have the following directories.
-Project
- src
- a.c
- b.c
- main.c
- headers
- a.h
- b.h
- build
- makefile
- project.exe
And here it's the makefile that I've done.
project: a.o b.o main.o
cc -o sesion0 a.o b.o main.o
a.o: ../src/a.c ../headers/a.h
b.o: ../src/b.c ../headers/b.h
main.o: ../src/main.c ../headers/a.h ../headers/b.h
But when I execute the make order, it tell's me that the file or directory a.o, b.o and main.o doesn't exist and also that there's not input files. In the end shows this error:
make: *** [project] Error 1
Does anyone know why this happen or where I have the error? I don't know very well how to manage the directories in the makefile.
Thanks.
Make has built-in rules for making x.o from x.c, but not from ../src/x.c. In other words, paths of input and output must be the same, only the file extension differs.
You can fix it by using VPATH for directory search:
VPATH = ../src:../headers
a.o: a.c a.h
b.o: b.c b.h
main.o: main.c a.h b.h
Related
I would like to let a target A depend on all dependencies of another target B, but not B itself.
My real project is not in C. I just use C to give an example.
I would like to save output messages during compilation of a.c in an output file a.out.
So the output file a.out should depend on dependency of normal compilation target a.o, but not a.o itself.
I would like to take the advantage that dependency of a.o can be generated automatically
and copy it to a.out automatically.
a.o : a.c
gcc a.c -o a.o
# a.out should depend on a.h b.h c.h, too. I would like to copy it from generated dependency below.
a.out : a.c
gcc a.c -o a.o > a.out
# Automatically generated
a.o : a.h b.h c.h
My Makefile compiles all the files everytime I run it though the files have not been changed. I know that this question has been asked several times but none of the provided solutions seem to work for me. I am new to Makefile and most of the times I do not understand the jargon used in the solution. Also, I want to save all the generated .o files under the folder 'obj'
Here is my folder structure
project (-)
gen (-)
display (-)
.c and .h files
logic (-)
.c and .h files
lib (-)
include (-)
.h files
.lib files
man (-)
.c and .h files
obj (-)
want to save all the .o files here
I am running this on Windows OS using MinGW
Here is my Makefile:
ALL: demo
SRCS:= filename1.o filename2.o filename3.o filename4.o and so on till filename27.o
demo: display.o logic.o man.o
gcc $(SRCS) -lglut32 -loglx -lopengl32 -Llib -o demo
display.o:
gcc -Igen/display -Igen/logic -Iman -Ilib/include gen/display/*.c -lglut32 -loglx -lopengl32 -Llib -c
logic.o:
gcc -Igen/display -Igen/logic -Iman -Ilib/include gen/logic/*.c -lglut32 -loglx -lopengl32 -Llib -c
man.o:
gcc -Igen/display -Igen/logic -Iman -Ilib/include man/*.c -lglut32 -loglx -lopengl32 -Llib -c
clean:
#echo "Cleaning up.."
-rm -rf *.o
-rm *.exe
NOTE: glut and oglx files are present in the lib folder. Display.o, lib.o and man.o do not have corresponding .c files. They are just folder names with many c files in them.
I understand this could be the problem. As there are no display.o, logic.o and man.o files created, MAKE complies the rule associated with it eveytime. SO how do I tell it to check for the actual .o filename1.o, filename2.o etc for the timestamp and recompile ONLY if they are older than the corresponding c files and h files maybe even the lib files they depend on.
I tried the following to create dependencies and avoid compiling of files everytime. But this did not help.
%.d: %.c
#set -e; rm -f $#; \
$(CC) -M $(CFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
At a basic level, make is looking for lines like:
target: dependency
command
If target does not exist, it calls the rule for dependency and then runs command. If target does exist, it tests if dependency is newer or does not exist. If so, it calls the rule for dependency and then runs command. Otherwise, it stops.
Significantly, the rule for dependency will only be called if (a) dependency doesn't exist, or (b) dependency is newer than target.
In the question, assume we run make demo. Then make looks for the line that begins demo: and notices it declares dependencies. So it looks at each dependency in turn to see if they require action. It first discovers display.o. It notices that display.o: does not exist, so it runs the associated rule. It does the same for the other *.o.
To avoid the *.o rules always being run because no associated file exists, you could rewrite like:
ALL: demo
SRCS:= filename1.o filename2.o filename3.o filename4.o and so on till filename27.o
demo: display.ts logic.ts man.ts
gcc $(SRCS) -lglut32 -loglx -lopengl32 -Llib -o demo
display.ts: gen/display/*.c
gcc -Igen/display -Igen/logic -Iman -Ilib/include gen/display/*.c -lglut32 -loglx -lopengl32 -Llib -c
echo . > display.ts
logic.ts: gen/logic/*.c
gcc -Igen/display -Igen/logic -Iman -Ilib/include gen/logic/*.c -lglut32 -loglx -lopengl32 -Llib -c
echo . > logic.ts
man.ts: man/*.c
gcc -Igen/display -Igen/logic -Iman -Ilib/include man/*.c -lglut32 -loglx -lopengl32 -Llib -c
echo . > man.ts
clean:
#echo "Cleaning up.."
-rm -rf *.o *.ts
-rm *.exe
Problem is that your binary object targets (like display.o) do not actually match files produced by their rules. If you tell make it needs to make target display.o, it (normally, except for phony targets, but those always rerun) expect the corresponding file to be produced by the rule's recipe and it can track if the target needs to be remade. If no such file is produces, this target always evaluates as outdated and needing remaking.
A bit of a silly example of this would be the following tree:
.
├── Makefile
├── main.c
└── test
└── file.c
and Makefile:
main: test.o main.o
$(CC) -o main *.o
test.o:
$(CC) $(CFLAGX) -c test/*.c
There is no test.o file and target needs to be remade... the rule runs, produces file.o (again). Since this target was remade and is prerequisite of main... everything always gets remade.
Now with this small modification:
main: test.o main.o
$(CC) -o main *.o
test.o:
$(CC) $(CFLAGX) -o $# -c test/*.c
test.o target indeed produces test.o file and the rule needs no remaking if test.c does not change... and with test.o unchanged and main.c perhaps as well, we get:
$ make
make: 'main' is up to date.
It still is not entirely correct as it really should read:
main: test.o main.o
$(CC) -o main $+
test.o: test/*.c
$(CC) $(CFLAGX) -o $# -c $^
Where I declare depend prerequisites of test.o and reference both them and the target by automatic variable in the rule's recipe. And Same goes for prerequisites for linking. Of course in this simple example I could just rely on implicit pattern rules and do this:
main: test/file.o main.c
test/file.o: test/*.c
What does this mean for your makefile? When you compile your object files, have a look what do they actually produce and match your target to that or (with -o $# for instance) tell them to produce exactly the file matching your target.
I've extended the silly example a bit and there are now two files in test/:
.
├── Makefile
├── main.c
└── test
├── file.c
└── other.c
And the Makefile can look something like this:
main: obj/file.o obj/other.o main.c
obj/%.o: test/%.c
mkdir -p obj
$(CC) $(CFLAGS) -c -o $# $^
It now stores object files in obj/ and make still understand what needs what and can track changes. Of course your setup is more complex and will require more rules, perhaps also divining actual sources or intermediate targets from the directory tree and define few variables to work with that information, e.g.:
OBJS := $(patsubst test/%.c,obj/%.o,$(wildcard test/*.c))
main: $(OBJS) main.c
obj/%.o: test/%.c
mkdir -p obj
$(CC) $(CFLAGS) -c -o $# $^
But the principles remain the same.
I have the following construct in the common make file which is to be included by
the module specific Makefile -
# Conditionally add Logger as a MUT dependency
define COND_ADD_LOGGER
$if($$(findstring -DLOGGER, $$(DEFINES)), SOURCES += logger.c)
endef
define CMN_TESTS_RULE
$(COND_ADD_LOGGER)
$(eval OBJECTS = $(SOURCES:.cpp=.o))
$(eval OBJECTS := $(OBJECTS:.c=.o))
$(TARGET): $(OBJECTS)
$(COMPILE_RULE_CMN)
endef
In my module's Makefile I do this -
SOURCES = a.c b.c test.cpp
TARGET = generic_tests
$(eval $(CMN_TESTS_RULE))
This isn't adding the logger.c files to the SOURCES list as I had expected.
(The DEFINES variable definitely has the sub-string "-DLOGGER" in it.)
This is the output when I use info -
$if($(findstring -DLOGGER, $(DEFINES)), SOURCES += logger.c)
generic_type_abstraction_tests: a.o b.o test.o
g++ -o $# $^ D:/TEST/gtest-1.7.0/make/gtest_main.a
$if($(findstring -DLOGGER, $(DEFINES)), SOURCES += logger.c)
generic_type_abstraction_tests: a.o b.o test.o
g++ -o $# $^ D:/TEST/gtest-1.7.0/make/gtest_main.a
I am using GNU Make version 3.81 from CYGWIN on a Windows 8 machine.
There are several things that do not make sense to me in your Makefile (especially strange use of nested eval). I suggest to fix them with something like:
# Conditionally add Logger as a MUT dependency
define COND_ADD_LOGGER
SOURCES += $(if $(findstring -DLOGGER,$(DEFINES)),logger.c)
endef
define CMN_TESTS_RULE
$(COND_ADD_LOGGER)
OBJECTS = $$(patsubst %.c,%.o,$$(patsubst %.cpp,%.o,$$(SOURCES)))
$(TARGET): $$(OBJECTS)
$(COMPILE_RULE_CMN)
endef
SOURCES = a.c b.c test.cpp
TARGET = generic_tests
$(eval $(CMN_TESTS_RULE))
.PHONY: debug
debug:
$(info SOURCES: $(SOURCES))
$(info OBJECTS: $(OBJECTS))
Demo:
$ make debug
SOURCES: a.c b.c test.cpp
OBJECTS: a.o b.o test.o
gmake: 'debug' is up to date.
$ make DEFINES=-DLOGGER debug
SOURCES: a.c b.c test.cpp logger.c
OBJECTS: a.o b.o test.o logger.o
gmake: 'debug' is up to date.
My directory contains 2 source files: a.c and b.c. I want to generate executable file a from a.c and b from b.c. Now I can only figure out one method to write Makefile:
all:
gcc -o a a.c
gcc -o b b.c
It seems a little awkward, is it better method?
The answers are fine, still I think you need some insight in how make works:
The basic functionality of make is to create output files from input files if necessary. make decides what is necessary by comparing timestamps: If any input file is newer than an output file created from it, the recipe for this output file is executed.
This means with just a rule named all, this rule is always executed (except when you happen to have a recent file actually called all -- to prevent this behavior, you have to list all as a .PHONY target, that is one that doesn't actually create a file). Your original Makefile is equivalent to a simple shell script, so it doesn't use make properly.
The minimal "correct" version of your Makefile should look like this:
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
.PHONY: all
So, all is "phony" and depends on a and b. a is only rebuilt when a.c changed, b is only rebuilt when b.c changed.
In a real project, your programs are probably made from more than just one source file and in this case, you can really take advantage of make: Have it build object files of your translation units, so only the parts that changed are actually rebuilt. It's overkill for your tiny example, but could e.g. look like this:
a_OBJS:= a.o
b_OBJS:= b.o
all: a b
a: $(a_OBJS)
gcc -o$# $^
b: $(b_OBJS)
gcc -o$# $^
%.o: %.c
gcc -c -o$# $<
clean:
rm -f *.o
.PHONY: all clean
You would just have to add more object files to a_OBJS and b_OBJS to include new translation units in your build. The pattern rule %.o: %.c will match them. There's a lot more to discover, I suggest starting with the GNU make manual.
I think the follow method is better:
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
In your version, make all will always run gcc twice, whether or not a.c and b.c are modified. In this version gcc will be run only when necessary.
Of course you can use some magic (for-loop or similar) to create the rules but I think the difference between my and your method is clear.
To me
all:
gcc -o a a.c
gcc -o b b.c
looks fine.
Or may be the following for better control
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
clean:
-rm a b
A lesser known trick to compile without makefile
make a #run cc -o a a.c by make or
make b #run cc -o b b.c by make
Or to generate both a and b
make a b
make uses implicit rule here, just like magic. But prefer a makefile with rule specified
I have this file:
main.c
A.h
A.c
B.h
B.c
X.h
and in main.c I include A and in A.h I include B and in B.h I include X.h
How could I write makefile for this? please tell me about dependency diagram of this example
Try this:
main: main.o A.o B.o
gcc -o main main.o A.o B.o
%.o: %.c
gcc -c $<
While compiling the .c files you don't have to worry about dependencies yet, only when linking the executable.