I would like to let a target A depend on all dependencies of another target B, but not B itself.
My real project is not in C. I just use C to give an example.
I would like to save output messages during compilation of a.c in an output file a.out.
So the output file a.out should depend on dependency of normal compilation target a.o, but not a.o itself.
I would like to take the advantage that dependency of a.o can be generated automatically
and copy it to a.out automatically.
a.o : a.c
gcc a.c -o a.o
# a.out should depend on a.h b.h c.h, too. I would like to copy it from generated dependency below.
a.out : a.c
gcc a.c -o a.o > a.out
# Automatically generated
a.o : a.h b.h c.h
Related
My directory contains 2 source files: a.c and b.c. I want to generate executable file a from a.c and b from b.c. Now I can only figure out one method to write Makefile:
all:
gcc -o a a.c
gcc -o b b.c
It seems a little awkward, is it better method?
The answers are fine, still I think you need some insight in how make works:
The basic functionality of make is to create output files from input files if necessary. make decides what is necessary by comparing timestamps: If any input file is newer than an output file created from it, the recipe for this output file is executed.
This means with just a rule named all, this rule is always executed (except when you happen to have a recent file actually called all -- to prevent this behavior, you have to list all as a .PHONY target, that is one that doesn't actually create a file). Your original Makefile is equivalent to a simple shell script, so it doesn't use make properly.
The minimal "correct" version of your Makefile should look like this:
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
.PHONY: all
So, all is "phony" and depends on a and b. a is only rebuilt when a.c changed, b is only rebuilt when b.c changed.
In a real project, your programs are probably made from more than just one source file and in this case, you can really take advantage of make: Have it build object files of your translation units, so only the parts that changed are actually rebuilt. It's overkill for your tiny example, but could e.g. look like this:
a_OBJS:= a.o
b_OBJS:= b.o
all: a b
a: $(a_OBJS)
gcc -o$# $^
b: $(b_OBJS)
gcc -o$# $^
%.o: %.c
gcc -c -o$# $<
clean:
rm -f *.o
.PHONY: all clean
You would just have to add more object files to a_OBJS and b_OBJS to include new translation units in your build. The pattern rule %.o: %.c will match them. There's a lot more to discover, I suggest starting with the GNU make manual.
I think the follow method is better:
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
In your version, make all will always run gcc twice, whether or not a.c and b.c are modified. In this version gcc will be run only when necessary.
Of course you can use some magic (for-loop or similar) to create the rules but I think the difference between my and your method is clear.
To me
all:
gcc -o a a.c
gcc -o b b.c
looks fine.
Or may be the following for better control
all: a b
a: a.c
gcc -o a a.c
b: b.c
gcc -o b b.c
clean:
-rm a b
A lesser known trick to compile without makefile
make a #run cc -o a a.c by make or
make b #run cc -o b b.c by make
Or to generate both a and b
make a b
make uses implicit rule here, just like magic. But prefer a makefile with rule specified
Is there any native makefile (GNU make, etc.) way to get prerequisites of target prerequisites? These question is not about dependency check from source files by compiler (g++ -MM, for example).
Can't find anything on subject. And as I can see, there is no special variables for this case.
To illustrate problem, here is my definition of compilation recipe from C++ source to object, pretty standard though:
##### UNIVERSAL COMPILE #####
%.o: %.cpp %.hpp
${CC} ${CFLAGS} -c $< -o $#
And then I need to build really big chains of dependencies:
a: a.o
b: b.o a.o
c: c.o b.o a.o
d: d.o c.o b.o a.o
etc, up to N times...
It is necessary because of this linking recipe:
##### UNIVERSAL LINK #####
%: %.o
${LN} ${LNFLAGS} $^ -o $#
As you can see, recipe takes all of supplied dependencies, but need to get all dependencies of all supplied dependencies.
There is no problem with overall program linking, as it is in recipe:
##### PROGRAM LINK ######
${BIN}: ${OBJ}
${LN} ${LNFLAGS} ${OBJ} -o ${BINDIR}/$#
But I need to do unit-testing, and units depends one on each others dependencies and hierarchy of testing for subsystems is very tiring to write as dependency chains that hard-coded.
Maybe I'm doing it in wrong way? Maybe there is alternatives to this link recipe? Thanks!
You're doing it in the wrong way. Why would you want to declare that b.o must be recompiled every time a.o changes (that's (one of) the things it means when you specify a prerequisite pf b.o : a.o)? That's not what needs to happen and it doesn't make sense.
You need to list all the object files as prerequisites of the single executable file, for example:
exe: a.o b.o c.o d.o ...
That's it.
I have this file:
main.c
A.h
A.c
B.h
B.c
X.h
and in main.c I include A and in A.h I include B and in B.h I include X.h
How could I write makefile for this? please tell me about dependency diagram of this example
Try this:
main: main.o A.o B.o
gcc -o main main.o A.o B.o
%.o: %.c
gcc -c $<
While compiling the .c files you don't have to worry about dependencies yet, only when linking the executable.
I would like to know if I can tell gcc/ld to omit unused modules from being put into the output file.
Suppose I have modules a.c, b.c and c.c. a.c and b.c depend on each other, one of them contains a main(), and due to whatever reasons, no parts of c.c are referenced.
gcc -c a.c
gcc -c b.c
gcc -c c.c
If I bundle the stuff together into a library, no code from c.c won't be in the output:
ar rcs abc.a a.o b.o c.o
gcc abc.a
But if I give the .o files directly to gcc, the code from c.c resp. c.o is included.
gcc a.o b.o c.o
Can I, by any way, tell gcc to leave out unused modules without putting them into a library?
I am programming an AVR µC and use AVR Studio, which doesn't allow the creation of libraries, but would like to omit the source files which are not used, depending on the build configuration.
I don't know if it's possible on AVR, but you could ask GCC to put each symbols in its own section using -ffunction-sections -fdata-sections at compile time. Then at link step, you could use -Wl,--gc-sections to ask ld to remove unused sections.
I want to make a simple makefile for a C project that have the following directories.
-Project
- src
- a.c
- b.c
- main.c
- headers
- a.h
- b.h
- build
- makefile
- project.exe
And here it's the makefile that I've done.
project: a.o b.o main.o
cc -o sesion0 a.o b.o main.o
a.o: ../src/a.c ../headers/a.h
b.o: ../src/b.c ../headers/b.h
main.o: ../src/main.c ../headers/a.h ../headers/b.h
But when I execute the make order, it tell's me that the file or directory a.o, b.o and main.o doesn't exist and also that there's not input files. In the end shows this error:
make: *** [project] Error 1
Does anyone know why this happen or where I have the error? I don't know very well how to manage the directories in the makefile.
Thanks.
Make has built-in rules for making x.o from x.c, but not from ../src/x.c. In other words, paths of input and output must be the same, only the file extension differs.
You can fix it by using VPATH for directory search:
VPATH = ../src:../headers
a.o: a.c a.h
b.o: b.c b.h
main.o: main.c a.h b.h