I have this file:
main.c
A.h
A.c
B.h
B.c
X.h
and in main.c I include A and in A.h I include B and in B.h I include X.h
How could I write makefile for this? please tell me about dependency diagram of this example
Try this:
main: main.o A.o B.o
gcc -o main main.o A.o B.o
%.o: %.c
gcc -c $<
While compiling the .c files you don't have to worry about dependencies yet, only when linking the executable.
Related
Suppose we have a.c b.c c.c .So the make file will like this
app: a.o b.o c.o
gcc -o app.o a.o b.o c.o
a.o: a.c
gcc -c a.c
b.o: b.c
gcc -c b.c
c.o: c.c
gcc -c c.c
In the future more C files may be added. So do I need to make target of .o extensions for each .c file. I got to know about suffix rules which uses the .source-extension.target-extension. But I could understand how to use this suffix rule in the make file. Please provide me the command to be included in make file and please describe the syntax.I am newbie to makefile.
You can use the below makefile.
app: a.o b.o c.o
gcc -o $# $^
a.o : a.h
b.o : b.h
c.o : c.h
%.o: %.c
gcc -c $<
Where $# is the target(app), $^ is the list of dependencies and $< is the corresponding c file to compile to object file
Below is the sample makefile for compiling c code.
TARGET = a.out
SRCS = a.c b.c c.c
OBJS = $(SRCS:.c=.o)
CFLAGS = -g -ggdb -O2 -Wall -Werror
CC = gcc
RM = rm
.PHONY: all clean
%.o : %.c
$(CC) $(CFLAGS) -c $< -o $#
$(TARGET) : $(OBJS)
$(CC) $^ -o $#
clean:
$(RM) *.o
$(RM) $(TARGET)
I'm trying to create a build system using make and would like to do the following:
have a list of source files specified in the makefile, e.g.
SOURCES = a.cpp b.cpp c.cpp
Automatically create build targets that depend on each file separately
I.e a single rule that would automatically expand into:
a.o: a.cpp
$(CC) $(CFLAGS) -c a.cpp -o a.o
b.o: b.cpp
$(CC) $(CFLAGS) -c b.cpp -o b.o
c.o: c.cpp
$(CC) $(CFLAGS) -c c.cpp -o c.o
I've tried the following:
SOURCES = a.cpp b.cpp c.cpp
OBJECTS = $(SOURCES:.cpp=.o)
$(OBJECTS): $(SOURCES)
$(CC) $(CFLAGS) -c $< -o $#
However, this seems to expand into the following
a.o: a.cpp b.cpp c.cpp
$(CC) $(CFLAGS) -c a.cpp -o a.o
b.o: b.cpp b.cpp c.cpp
$(CC) $(CFLAGS) -c a.cpp -o b.o
c.o: c.cpp b.cpp c.cpp
$(CC) $(CFLAGS) -c a.cpp -o c.o
Which is not right
Is there a simple way to achieve the result that i wrote earlier?
Make already has built-in rules that convert a .cpp file to a .o file. Just write:
SOURCES = a.cpp b.cpp c.cpp
all: $(SOURCES:.cpp=.o)
and it will work. If you want to know how to write your own rules, read about implicit rules, in particular pattern rules.
Say that I have two variables in Makefile
CXXFILES = a.cpp b.cpp
OBJFILES = a.o b.o
I would like to write a rule that will expand to
a.cpp : a.o
g++ -o a.o a.cpp
b.cpp : b.o
g++ -o b.o b.cpp
Note that I'm not looking for
%.o : %.cpp
g++ -o $# $<
because I don't want to match all .cpp files -- I only want those files specified by a variable.
Sounds like a job for a Static Pattern Rule:
Here is an example, which compiles each of foo.o and bar.o from the
corresponding .c file:
objects = foo.o bar.o
all: $(objects)
$(objects): %.o: %.c
$(CC) -c $(CFLAGS) $< -o $#
Suppose I have these following c++ files, how should I write a basic makefile for them (using g++)?
a.cpp a.h, b.cpp b.h, c.cpp c.h, main.h
When b.h includes a.h, c.h includes b.h and main.h includes c.h?
thanks a lot
so you can write.
EXE := exe
CC := g++
CPP_FILES := a.cpp b.cpp c.cpp
HPP_FILES := a.h b.h c.h main.h
$(EXE) : $(CPP_FILES) $(HPP_FILES)
$(CC) -o $# $(CPP_FILES)
.PHONY : clean
clean:
rm -rf $(EXE) *.o
How to compile a file? Say you have test.cpp and test.h now, to compile and link it:
g++ -c test.c
g++ -o test test.o
Easiest Makefile:
test: test.o #means test depends on test.o
g++ -o test test.o
test.o: test.cpp test.h #means test.o depends on test.cpp and test.h
g++ -c test.cpp
#if you want clean? add below line too.
clean:
rm test test.o
If your app depends on multiple files, then
test: test1.o test2.o test3.o #means your app depends on test1.o test2.o and test3.o
g++ -o test test1.o test2.o test3.o
test1.o: test1.cpp test1.h
g++ -c test1.cpp
test2.o: test2.cpp test2.h
g++ -c test2.cpp
...
I want to make a simple makefile for a C project that have the following directories.
-Project
- src
- a.c
- b.c
- main.c
- headers
- a.h
- b.h
- build
- makefile
- project.exe
And here it's the makefile that I've done.
project: a.o b.o main.o
cc -o sesion0 a.o b.o main.o
a.o: ../src/a.c ../headers/a.h
b.o: ../src/b.c ../headers/b.h
main.o: ../src/main.c ../headers/a.h ../headers/b.h
But when I execute the make order, it tell's me that the file or directory a.o, b.o and main.o doesn't exist and also that there's not input files. In the end shows this error:
make: *** [project] Error 1
Does anyone know why this happen or where I have the error? I don't know very well how to manage the directories in the makefile.
Thanks.
Make has built-in rules for making x.o from x.c, but not from ../src/x.c. In other words, paths of input and output must be the same, only the file extension differs.
You can fix it by using VPATH for directory search:
VPATH = ../src:../headers
a.o: a.c a.h
b.o: b.c b.h
main.o: main.c a.h b.h