VHDL LFSR Output through FPGA board SMA connector - vhdl

Question

I recently started working on an FPGA project for school, I have never worked with VHDL before so I tried my best to piece my program together. Overall, my goal is to make a prbs or LFSR to generate randomly. My vhdl code checks out in xilinx ISE software and runs in testbench fine but I need to flash the project to the board and connect an oscilloscope to one of the SMA connectors on the board, My question is how can I i forward my outputs to a single SMA connector on the Spartan 6 board
library IEEE;
use IEEE.std_logic_1164.all;
entity LFSR is
port (
clock : std_logic;
reset : std_logic;
data_out : out std_logic_vector(9 downto 0)
);
end LFSR;
architecture Behavioral of LFSR is
signal lfsr_reg : std_logic_vector(9 downto 0);
begin
process (clock)
variable lfsr_tap : std_logic;
begin
if clock'EVENT and clock='1' then
if reset = '1' then
lfsr_reg <= (others => '1');
else
lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);
lfsr_reg <= lfsr_reg(8 downto 0) & lfsr_tap;
end if;
end if;
end process;
data_out <= lfsr_reg;
end Behavioral;
Now I just want to forward the output/outputs to an SMA connector so I can get the results on the oscilloscope, any help would be great

Answer 1

You just need to map your I/Os to actual pins on your FPGA chip. This is done in a constraints file (typically a .ucf), which you can either hand-edit (it's just text), or let a tool handle for you.
In the newer ISE tools PlanAhead is responsible for this - you can open it from the ISE Processes Pane (select User Constraints -> I/O Pin Planning (PlanAhead) - Post-synthesis).
This opens PlanAhead and gives you a list of the I/Os in your design (your clock, reset and data_out). Now you just need to map these to the correct FPGA pins. Have a look in your board documentation to find the locations of your clock-input, push-buttons (for reset) and SMA connector.
PlanAhead should create the .ucf file for you, and add it to your project. Afterwards you can edit it in the ISE editor - it's pretty self-explanatory once you have some initial content in it.
Also, check out this Xilinx guide (from page 100 and onwards) for a step-by-step guide.

Answer 2

Your SMA connector can only hold a single output, not a bus.
To see the MSB of your LFSR just add the following lines to your .ucf file:
NET clock LOC = $PIN;
NET reset LOC = $PIN;
NET dataout<9> LOC = $PIN; # your SMA output
NET dataout<8> LOC = $PIN;
NET dataout<7> LOC = $PIN;
NET dataout<6> LOC = $PIN;
NET dataout<5> LOC = $PIN;
NET dataout<4> LOC = $PIN;
NET dataout<3> LOC = $PIN;
NET dataout<2> LOC = $PIN;
NET dataout<1> LOC = $PIN;
NET dataout<0> LOC = $PIN;
See in your board documentation (or schematic) for the right pins and add the right pin names in your .ucf file.
I suggest to use some LEDs for the remaining outputs of dataout.