block ram (BRAM) read and write using different clocks - vhdl

Question

I am relatively new to some advanced VHDL programming and have a problem i have been facing for a while.
I will try to be very thorough in my problem description.
I am using a Digilent Nexys-3 board with SPARTAN - 6 FPGA
Here is what i am trying to implement:
Read data from ADC SPI bus and store it into the BRAM.
For this i instantiate a block RAM using a memory IP core generator
ADC_BRAM: bram
port map( ..
..
addra => addra,
dina => ADC_DATA,
..
..
);
The addra, ADC_DATA (data on SPI bus stored into a std_logic_vector) is assigned during the "read_adc" state of the FSM in the ADC module.
After the ADC has sampled 100 points I stop writing into the BRAM
main: process(clk)
begin
if(rising_edge(clk)) then
case state is
when read_adc =>
.....
.....
.....
if(addra < "1100100") then
.....
<some code>
addra <= addra + 1;
.....
elsif (addra = "1100100") then
state <= endofconversion;
end if;
when endofconversion =>
addra <= "00000000";
wea <= "0"; -- write enable for BRAM
state <= read_bram;
Next, i want to access the data from the BRAM and send it using USB-UART.
From what i understand all the BRAM's are synchronous and thus have to be implemented with process(clk,reset).
Currently i have implemented the state " read_bram" under the same process as mentioned above
main: process(clk)
begin
if(rising_edge(clk)) then
case state is
<some code>
when endofconversion =>
addra <= "00000000";
wea <= "0"; -- write enable for BRAM
state <= read_bram;
when read_bram =>
....
<some code>
....
end case;
Now the UART clock needs to be much slower than the rate at which ADC has been read.
My question is " How do i implement the read operation of the BRAM using a much slower clock, which will ensure proper functioning of the UART" ?
I also tried another approach where the BRAM module is defined in the top level file and i send the " addra, ADC_DATA" generated from the ADC module into the port map of the BRAM module.
Now, on the top level if i create a slower clock to read the data ("douta") from the BRAM and send it to UART, i need to generate "addra" in this process and send it to BRAM port "addra"
This causes issues of " multiple drivers " connected to signal "addra", as its values changes in the "process()" of both the ADC module (faster clock) and the top level module (slower clock).
Please help me out. I can provide more info if the problem description is not clear.
TLDR; How can i use 2 separate clocks while implementing synchronous memory BRAM
- "faster clock => write into BRAM" -- based on ADC sampling rate
- " slower clock => read from BRAM" -- based on UART clk (slower BAUD rate than ADC sampling speed)