There is a logical address space of 8 pages, and each page is 2KB.
The physical address space has 4 frames (size of a frame equals the size of a page).
I am given a sketch where there is an arrow from page number 0 to frame 1 that indicate a mapping between page 0 to frame 1.
I need to find the physical address of the logical address 2500.
I would like to know if my solution is correct.
This is my solution:
Because a size of a page is 2KB, that means that we need 14 bits for the offset. (cause 2KB=2^14)
And there are 8 pages (0 to 7) so we need 3 bits for the page number.
So the given virtual address in binary is:
000 00100111000100 =2500
first 3 bits from left - 000 - indicates page number 0
the rest of the bits - 00100111000100 - indicates the offset 2500
page 0 ----->frame 1 (mapping in the sketch)
So my physical address will be:
0100100111000100 = 18884.
first 2 bits -indicate the frame number- 01.
rest of the bits - indicates the offset - 00100111000100.
(there are 4 frames and therefor we need 2 bits for frame number).
I ll appreciate a response.
Thanks,
Shiran
2KB = 2^1 * 2^10 = 2^11 ---> 11 Bits, Not 14
The logic address is continuous, and you can follow steps
(1) calculate 2500/(2*1024)
the quotient is 1 --> page no. of logic address
the remainder is 452 --> offset of logic address
-->same is offset of physical address
(2) find frame no. of physical address page no. (ie, 1 from above calculation) of logical address refers to. Unfortunately the mapping is not given in the question. Let's assume page 1 in logic address is mapped into frame 4 in physical address.
(3) the physical address is [frame no.]*[frame full length] + offset, i.e.,
4*(2*1024)+452 = 8644 or 0010000111000100 (binary) or 21c4(H).
Hope it helps.
Related
This question is mostly just to clarify my understanding.
Say I have a 32-bit Computer, with virtual memory space of 2^32 bytes.
Memory paging is used, each page is 2^8 bytes.
So the memory address sizes are 24 bits. Since (2^32/2^8 = 2^24 bytes).
And the offset would be 8 bits? This I do not quite understand. Since I know that the total address is 32, and 24 is already taken by the pages, so the remainder is the offset of 8.
Lastly for the page size. If each physical memory address is stored in 32 bits (4 bytes), the table size would be 2^26 (2^24 * 2^2). Is this correct?
Page Table size = number of entries*size of entry
In your case, each page is 2^8 bytes, that is - you need 8 bits offset. You got that one right.
This leaves us with 24 bits for Page. 2^24 different pages.
Size of page-table for process X is: 2^24*Entry-Size. which is not provided by you here.
Lets assume it needs 32 bits per entry. Then, 2^24*32 = 2^24*2^5 = 2^29 bits.
I had operating exam a week a go and I faced the following question:
I solved the first part in this way :
2^32/2^12=2^20 * 4 =4* 2^20 size of page table
First I want to see if my answer is right? then for the second part I have no Idea how to solve it I read chapter 8 of operating system concept but could not get any idea how to solve it...
Can anyone help?
The question talks about two cases:
1st Case: When single level paging is enabled (1st Question)
2nd Case: When two level paging is enabled (2nd question)
(Refer this link to see how two-level paging is perceived graphically )
Now, to get the size of page-table we need Number of Page-Table Entries and Size of each entry and we multiply it to get size of page table.
Given, Size of page-table entry - 4 Bytes
For Question 1:
Given, Size of virtual memory: 2^32 bytes
Size of each page: 2^12 bytes
So, Max number of pages that virtual mermory can allocate: 2^(32-12) - 2^20 pages
This means, in a case of single level paging page table will consists of 2^20 page table entries.
Currently, we have number of page table entries and size of each page table entry which consitute size of single level page-table i.e
**2^20(page-table entries) * 4 ( size of each page-table entry in bytes)**
2nd Question:
The statement says that page-size used for paging the page-table is 2^12 bytes which means single-level page-table is further divided into blocks of 2^12 bytes each which means after dividing the page-table into 2^12 bytes blocks we, get
( 2^20 * 4 ( size of page table ) ) / ( 2 ^ 12 ( block size) ) = 2 ^ 10 page-tables
2^10 page tables can be formed at maximum.
To, find the size of 2nd level page table we need numer of entries and size of each page-table entry.
Number of entries are 2 ^ 10 as found above.
Size of each page table entry will be 10 bits which has to be converted into bytes, so we have to make it 16 bits to make it two bytes and size of second page - table will be
2 ^ 10 * 2
This is the answer to the second question
Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.
Hi,
In order to use large size page table hierarichal paging is done .
In case of two level page table scheme . for :
logical address space - 32bit - 2^32
page size - 4kb i.e 2^12
In one level :
page number - 20bit calculated as (32 - 12)
page offset - 12 bit
Now, In two level :
again, page number - 20bit is split into pagenumber(second level) and page offset .also
the address space is (2^20)
considering again page size of 4kb - (2^12)
so page number(second level ) should be calculated as : (20 - 12 ) - 8bits
and page offset : 12 bits.
But, It is mentioned that page number is divided evenly :
i.e page number p1 - 10 bits
page number p2 - 10 bits
page offset d - 12bits.
Why is the second level pagenumber divided evenly ? Is it that this division done
arbitarily according the requirement ? Is there no specific method for dividing as in case of single-level page table ?
Any help will be valuable .
Thanks,
Tazim
With 4 KB pages, the last 12 bits are the offset into the page. That leaves 20 bits for a 32 bit address. These 20 bits are used as an index into the page tables, not an offset. By splitting them evenly between the 2 levels, the tables are both the same size. The first table specifies the address of the second table, and the second table specifies the physical address of the page. 10 bits for each index means 1024 entries in each table. This is very convenient because it means each table is exactly 1 page when using 32 bit entries.
Example: Take the address 0x00FF1234. The binary representation of this address is 00000000111111110001001000110100. By splitting this up, we get 0000000011 1111110001 001000110100, or 0x3 0x3F1 0x234. So item 3 in the first level table gives the address of the second level table, item 0x3F1 in the second table gives the address of the page used, and the address is 0x234 bytes into that page.
This blog series has a very indepth set of examples for how the page table works, how to convert virtual<->physical addresses and such.
Here's an exerpt;
It is obvious that the offset takes 12 bits.
When the size of each entry is 4bytes, you get result that 10 bits for outer page table and 10 bits for inner table table. The calculation is as following:
(2^20 entries × 4 bytes/entry)/4k bytes = 2^10 --> outer page table should have 10 bits
(space taken by page table)/frame(or page)size = no. of inner page tables
4k bytes/4 bytes = 2^10 --> inner page table should have 10 bits
(size of pages in page table)/size of entries = no. frames
That how it gets 10 bits and 10 bits evenly. For different situation, it is not necessary to have even distribution.
I'm reading the "Modern Operating System" book. And I'm confused about the "Page Size".
In the book, the author says,
The incoming 16-bit virtual address is
split into a 4-bit page number and
12-bit offset. With 4 bits for the
page number, we can have 16 pages, and
with 12 bits for the offset, we can
address all 4096 bytes within a
page.
Why 4096 bytes? With 12 bits, we can address 4096 entries within a page, correct. But, one entry is an address (in this case, address size = 16 bits). So I think we can address 4096(entry) * 16(bit) = 4096(entry) * 2(byte) = 8KB, but why the book says that we can address 4096 (bytes) ?
Thanks in advance! :)
This is assuming byte-addressed memory (which almost every machine made in the past 30 years uses), so each address refers to a byte, not an entry or address or any other larger value. To hold a 16-bit value, you'll need two consecutive addresses (two bytes).
More than 30 years ago, there used to be machines which were word addressed, which worked like you surmise. But such machines had a tough time dealing with byte-oriented data (such as ASCII characters), and so have fallen out of favor. Nowadays, things like byte addressability, 8-bit bytes and twos-complement integers are pretty much just assumed.
The 12 bits are an offset within a page. The offset is in bytes, not addresses. 2^12 is 4096.
Because with 12 bit, we can address 2^12=4096 slots. Each slot represents an address which size is 1 byte in byte-addressable memory. Hence the total size is 4096*1=4096 bytes = 4KB.
What you are calculating is the page size, i.e. the size of a page in the page table in the memory. As we use 12 bits for the offset, each frame in the physical memory is 2^12=4096K. However, each page in the page table occupies 2^12 entries x 2 bytes = 8K in the memory.
okay so you have 16 bit virtual address let see what does it mean .It means you have 2**16 =65536 bytes.
4 bit page number that means there are 16 pages as 2^4=16
Now You Name The Pages As page1,page2...page16.
Now We are left with 12bits let us see how many address can 12 bits represent 2**12=4096 bytes
65536 bytes could also be achieved by dividing it into 16 pages containing 4096 bytes each as 4096*16=65536