I had operating exam a week a go and I faced the following question:
I solved the first part in this way :
2^32/2^12=2^20 * 4 =4* 2^20 size of page table
First I want to see if my answer is right? then for the second part I have no Idea how to solve it I read chapter 8 of operating system concept but could not get any idea how to solve it...
Can anyone help?
The question talks about two cases:
1st Case: When single level paging is enabled (1st Question)
2nd Case: When two level paging is enabled (2nd question)
(Refer this link to see how two-level paging is perceived graphically )
Now, to get the size of page-table we need Number of Page-Table Entries and Size of each entry and we multiply it to get size of page table.
Given, Size of page-table entry - 4 Bytes
For Question 1:
Given, Size of virtual memory: 2^32 bytes
Size of each page: 2^12 bytes
So, Max number of pages that virtual mermory can allocate: 2^(32-12) - 2^20 pages
This means, in a case of single level paging page table will consists of 2^20 page table entries.
Currently, we have number of page table entries and size of each page table entry which consitute size of single level page-table i.e
**2^20(page-table entries) * 4 ( size of each page-table entry in bytes)**
2nd Question:
The statement says that page-size used for paging the page-table is 2^12 bytes which means single-level page-table is further divided into blocks of 2^12 bytes each which means after dividing the page-table into 2^12 bytes blocks we, get
( 2^20 * 4 ( size of page table ) ) / ( 2 ^ 12 ( block size) ) = 2 ^ 10 page-tables
2^10 page tables can be formed at maximum.
To, find the size of 2nd level page table we need numer of entries and size of each page-table entry.
Number of entries are 2 ^ 10 as found above.
Size of each page table entry will be 10 bits which has to be converted into bytes, so we have to make it 16 bits to make it two bytes and size of second page - table will be
2 ^ 10 * 2
This is the answer to the second question
Related
I was reading here and at the problem 3, exercise 2 he states:
The top-level page table should not assume that 2nd level page tables are page-aligned. So, we store full physical addresses there. Fortunately, we do not need control bits. So, each entry is at least 44 bits (6 bytes for byte-aligned, 8 bytes for word-aligned). Each top-level page table is therefore 256*6 = 1536 bytes (256 * 8 = 2048 bytes).
So, why does first layer can't assume page aligned 2nd layer?
Since it's presumes that the memory is not allocated in page granularity, wouldn't that make the allocation significantly more complicated?
I have tried btw to read the lectures of the course but they are that comprehensive.
I have a HW problem for my architecture class about determining page table size. I see that there is already a SO entry about this here:
Determine page table size for virtual memory
But I am having trouble applying that to my problem.
I understand that the general equation is:
(Total # pages) x (size of page)
But when I do the math the numbers don't make sense. Could somebody please help me see what I am doing wrong?
byte-addressable memory,
48 bit virtual space,
16 kB page size (14 bits to represent),
4 GB physical memory (22 bits to represent), &
Valid, dirty, reference bits for each page
What is the table size for one application?
Total # pages = 2^48 / 2^14 = 2^34
Page size = 16 kB
Total page size = (total # pages) x (page size) = 2^34 x 16 kB = 274877906944 kB ?!?!?
Some help would be much appreciated - there is clearly something I am doing wrong.
Thank you.
You confuse the page with a page table entry:
The page table consists of page table entries
Each page table entry holds an address to physical memory of a page
The page is a 16kB slice of memory
You want to map 4GB of physical memory onto a number of 16kB pages.
So you need (4*10^6 / 16*10^3) = 250 pages (adresses)
Each address is held in a page table entry which is a 32-bit integer that consists of the address in physical memory of a page and some modifier/info bits about that page.
Each process needs atleast one page table. Here it consists of 250 page table entries. Each page table entry size is an 32-bit (4B) number (call it whatever you want)
So the total size needed for one process is:
250 * 4B = 1000 B = 1kB
Why this approach isn't used based on the paging model used by the x86 MMU:
The problem with a one single level paging mechanism as you describe is that every (no matter how small) process will need:
4GB/16kb = 4 * 10^6 B / 16 * 10^3 B = 0,25 * 1000 = 250 page table entries
250 * 4 byte (32 bit per entry) = 1 kB per process
It doesn't seem like much but here you have used 16 kB pages (for example most x86 systems use 4kb pages so you would need 1MB for each process)
This is why the x86 uses a two-level paging process in which each process has 1024 page directory entries and each of those entries hold the address of the page table (which holds 1024 page table entries). So the minimal allocated memory of a process becomes:
4 bytes (page directory entry) + 1024 * 4 bytes (1024 32-bit page table entries)
Each page table entry points to a 4kB physical page in memory.
1024 page directory entries * 1024 page table entries for each directory * 4kB page = 4GB of addressable memory
The virtual address consists is roughly:
Page directory entry index
Page table entry index
Offset in the 4kB page
This means that even if you increase the size of a single page (thus reducing the number of page table entries needed) then you need a bigger number to describe the offset.
A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table
organization. The page table base register stores the base address of the first-level table (T1), which
occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2).
Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page
table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set
associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
Q.What is the size of a page in KB in this computer?
(A) 2 (B) 4 (C) 8 (D) 16
Q.What is the minimum number of page colours needed to guarantee that no two synonyms map to
different sets in the processor cache of this computer?
(A) 2 (B) 4 (C) 8 (D) 16
A question from last Gate exam . how do I solve this kind of question?
All the page table reside in the physical memory(RAM)
since the physical address is 32 bit addressable each level table holds a 32 bit
(4 byte)address of the RAM
Assume the size of a page is x bytes. (which we need to find)
As the size of level 1 table is also x (as given in the question that level 1 table accommodate exactly a page)it can hold x/4 base addresses of x/4 level 2 tables (which also accommodate exactly a page) and each level 2 table hold base addresses of x/4 level 3 tables.
the level 3 table has entities equal to 2^46/x
ie. (x/4)(x/4)(x/4) = 2^46/x
on solving x=8192 which is in bytes
so 8192/1024 = 8 K bytes
answer to 2nd part .... as its virtually indexed and physically tagged so for caches L group bits and B byte bits can accommodate a Full page of Ram for the efficient use so for efficient use we have
cache size /2^A = 2^l+b =page size ................http://cseweb.ucsd.edu/classes/fa10/cse240a/pdf/08/CSE240A-MBT-L18-VirtualMemory.ppt.pdf
Page size = 1 MB /16 = 64 KB .........
so cache will have 8 different pages copied on same l+b bits
so we will color 8 Pages to differentiate between them.
Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.
Hi,
In order to use large size page table hierarichal paging is done .
In case of two level page table scheme . for :
logical address space - 32bit - 2^32
page size - 4kb i.e 2^12
In one level :
page number - 20bit calculated as (32 - 12)
page offset - 12 bit
Now, In two level :
again, page number - 20bit is split into pagenumber(second level) and page offset .also
the address space is (2^20)
considering again page size of 4kb - (2^12)
so page number(second level ) should be calculated as : (20 - 12 ) - 8bits
and page offset : 12 bits.
But, It is mentioned that page number is divided evenly :
i.e page number p1 - 10 bits
page number p2 - 10 bits
page offset d - 12bits.
Why is the second level pagenumber divided evenly ? Is it that this division done
arbitarily according the requirement ? Is there no specific method for dividing as in case of single-level page table ?
Any help will be valuable .
Thanks,
Tazim
With 4 KB pages, the last 12 bits are the offset into the page. That leaves 20 bits for a 32 bit address. These 20 bits are used as an index into the page tables, not an offset. By splitting them evenly between the 2 levels, the tables are both the same size. The first table specifies the address of the second table, and the second table specifies the physical address of the page. 10 bits for each index means 1024 entries in each table. This is very convenient because it means each table is exactly 1 page when using 32 bit entries.
Example: Take the address 0x00FF1234. The binary representation of this address is 00000000111111110001001000110100. By splitting this up, we get 0000000011 1111110001 001000110100, or 0x3 0x3F1 0x234. So item 3 in the first level table gives the address of the second level table, item 0x3F1 in the second table gives the address of the page used, and the address is 0x234 bytes into that page.
This blog series has a very indepth set of examples for how the page table works, how to convert virtual<->physical addresses and such.
Here's an exerpt;
It is obvious that the offset takes 12 bits.
When the size of each entry is 4bytes, you get result that 10 bits for outer page table and 10 bits for inner table table. The calculation is as following:
(2^20 entries × 4 bytes/entry)/4k bytes = 2^10 --> outer page table should have 10 bits
(space taken by page table)/frame(or page)size = no. of inner page tables
4k bytes/4 bytes = 2^10 --> inner page table should have 10 bits
(size of pages in page table)/size of entries = no. frames
That how it gets 10 bits and 10 bits evenly. For different situation, it is not necessary to have even distribution.