Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.
Related
I was reading here and at the problem 3, exercise 2 he states:
The top-level page table should not assume that 2nd level page tables are page-aligned. So, we store full physical addresses there. Fortunately, we do not need control bits. So, each entry is at least 44 bits (6 bytes for byte-aligned, 8 bytes for word-aligned). Each top-level page table is therefore 256*6 = 1536 bytes (256 * 8 = 2048 bytes).
So, why does first layer can't assume page aligned 2nd layer?
Since it's presumes that the memory is not allocated in page granularity, wouldn't that make the allocation significantly more complicated?
I have tried btw to read the lectures of the course but they are that comprehensive.
I had operating exam a week a go and I faced the following question:
I solved the first part in this way :
2^32/2^12=2^20 * 4 =4* 2^20 size of page table
First I want to see if my answer is right? then for the second part I have no Idea how to solve it I read chapter 8 of operating system concept but could not get any idea how to solve it...
Can anyone help?
The question talks about two cases:
1st Case: When single level paging is enabled (1st Question)
2nd Case: When two level paging is enabled (2nd question)
(Refer this link to see how two-level paging is perceived graphically )
Now, to get the size of page-table we need Number of Page-Table Entries and Size of each entry and we multiply it to get size of page table.
Given, Size of page-table entry - 4 Bytes
For Question 1:
Given, Size of virtual memory: 2^32 bytes
Size of each page: 2^12 bytes
So, Max number of pages that virtual mermory can allocate: 2^(32-12) - 2^20 pages
This means, in a case of single level paging page table will consists of 2^20 page table entries.
Currently, we have number of page table entries and size of each page table entry which consitute size of single level page-table i.e
**2^20(page-table entries) * 4 ( size of each page-table entry in bytes)**
2nd Question:
The statement says that page-size used for paging the page-table is 2^12 bytes which means single-level page-table is further divided into blocks of 2^12 bytes each which means after dividing the page-table into 2^12 bytes blocks we, get
( 2^20 * 4 ( size of page table ) ) / ( 2 ^ 12 ( block size) ) = 2 ^ 10 page-tables
2^10 page tables can be formed at maximum.
To, find the size of 2nd level page table we need numer of entries and size of each page-table entry.
Number of entries are 2 ^ 10 as found above.
Size of each page table entry will be 10 bits which has to be converted into bytes, so we have to make it 16 bits to make it two bytes and size of second page - table will be
2 ^ 10 * 2
This is the answer to the second question
(well, actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.)
I have recently started learning computer organisation and architecture. I have gained fair understanding for how caches are organised, how mapping between cache and main memory takes place (direct , fully and set-associative mapping), what is a page table(what are pages, blocks etc.), i can that say I have basic knowledge of segmentation , paging, virtual address and physical addresses.( at the basic level ofcourse).
well I have come across this question:
A computer has 46-bit virtual address ,32- bit physical address, and a three level
page table organisation. The page table base-register stores the base address of the
first level table(t1), which occupies exactly one page.Each entry of t1 stores the base
address of the page of second level table t2. Each entry of t2 stores the base address
of the page of the third level table t3. Each entry of t3 stores a page table entry
(PTE). The PTE is 32 bit in size. The processor used in the computer has a 1MB
16-way set associative virtually indexed physically tagged cache. The cache block size
is 64 Bytes.
First of all I am facing difficulty in just imagining such type of a virtual computer.
can any one help me by giving a simple steps on How to realize such a virtual computer on paper, or just how to understand what is given in the question. What is really asked??
How would one represent a computer having a 46-bit virtual address and having three level page table.
what is virtually indexed and physically tagged cache.
After reading what is given above , I feel that I just know the terms but I am unable to relate them together to solve problems.
I will be glad If someone tries to explain how my thought process should be understand and apply these concepts practically to solve such types of problems.
some questions based on the above paragraph:
1) What is the size of a page in KB in this computer?
2) what is the minimum number of page colours needed to guarantee that no two synonyms
map to different sets in the processor cache of this computer?
A good resource where such problems are actually taught to solve will a appreciated.
Good articles and views are most welcome.
Thankyou in advance !!
We know that all levels page tables must be completely full except outermost, outermost page table may occupy whole page or less. But in question it is given that Outermost page table occupy whole page.
Now let page size is 2 Bytes.
Given that PTE = 32 bits = 4 Bytes = 22 Bytes.
Number of entries in any page of any pagetable =page size/PTE = 2p/22 = 2p-2.
Therefore Logical address split is
|---------------------|------------------|---------------------|-------------|
| p-2 | p-2 | p-2 | p |
|---------------------|------------------|---------------------|-------------|
logical address space is 46bits given.
Hence equation becomes,
(p-2)+(p-2)+(p-2)+p = 46
⇒p=13.
There fore page size is 213 Bytes =8KB.
I can help you with the first question.
Let page size is 2^x. Each entry of T1 is 32 bits means 4 bytes. Total size is 2^X bytes(1 page). T1 contains 2^X / 4 = 2^(X-2) entries.
So we use first X-2 bits of the 46 bit virtual address to index into one entry in T1. It gives the address of one T2.
T2 also contains 2^(X-2) entries.( same way as T1). So we use next X-2 bits to index into T2 and get the address of a T3.
It is given each entry of T3 is 32 bytes (including flags and all). Total size of 1 page = 2^X bytes. No of entries is 2^(X-2). So again we use X-2 bits to index into T3 and get the staring adress of frame.
Then we need the offset. Since the page size is 2^X, offset is X bits long.
First (x-2) bits gives address of T2.
Next (x-2) bits gives address of T3.
Next (x-2) bits gives address of Frame from T3.
Remaining x bits give offset in frame.
Total is 46 bits
x-2 + x-2 + x-2 + X = 46
4X - 6 = 46
X =13
Page Size = 2^13 bytes.
Consider a virtual memory system with 32-bit virtual addresses and 1KB pages. Each page table entry requires 32-bits. It is desired to limit the page table size to one page.
How many levels of page tables are required?
Tables at two of the levels have 256 entries;tables at one level
have 64 entries.(8+8+6=22). If the top level page table has 2^6
entries then how many pages are possible?
If middle level page table has 2^6 entries then how many pages are
possible ?
If bottom level page table has 2^6 entries then how many pages are
possible ?
There are 2^32/2^10 = 2^22 pages on such a system. This means that only 22-bits are needed to address a page. For simplicity and practicality, most modern systems would align that to 32-bits and use the extra bits as flags, so at 32-bit page table entries there are 16 MB in page table addresses. A single page can hold 256 entries, necessitating a total number of pages to 2^22 / 256 = 16384 for the deepest level. The next level would then have 16384 / 256 = 64; The highest level would fit on one page, since 64 < 256, and therefore the answer is 3.
If you disgregard 32-bit alignment (which would be untenable in real world scenarios), then the answer is still three, since at 22-bits there are a maximum of 372 entries per page and therefore, 2^22/ 372 = 11275 for the first and 11275 / 372 = 30 for the second, and 1 for the third.
Alternatively you could interpret it from top to bottom, so instead of starting from the deepest level you start from the top level. In this particular case, starting from the top will lead to the deepest level having the most unused entries per page. This is obviously not ideal and it is better to have unused page table entries at higher levels.
With either of these interpretations, however, the answer is unequivocally 3.
Hi,
In order to use large size page table hierarichal paging is done .
In case of two level page table scheme . for :
logical address space - 32bit - 2^32
page size - 4kb i.e 2^12
In one level :
page number - 20bit calculated as (32 - 12)
page offset - 12 bit
Now, In two level :
again, page number - 20bit is split into pagenumber(second level) and page offset .also
the address space is (2^20)
considering again page size of 4kb - (2^12)
so page number(second level ) should be calculated as : (20 - 12 ) - 8bits
and page offset : 12 bits.
But, It is mentioned that page number is divided evenly :
i.e page number p1 - 10 bits
page number p2 - 10 bits
page offset d - 12bits.
Why is the second level pagenumber divided evenly ? Is it that this division done
arbitarily according the requirement ? Is there no specific method for dividing as in case of single-level page table ?
Any help will be valuable .
Thanks,
Tazim
With 4 KB pages, the last 12 bits are the offset into the page. That leaves 20 bits for a 32 bit address. These 20 bits are used as an index into the page tables, not an offset. By splitting them evenly between the 2 levels, the tables are both the same size. The first table specifies the address of the second table, and the second table specifies the physical address of the page. 10 bits for each index means 1024 entries in each table. This is very convenient because it means each table is exactly 1 page when using 32 bit entries.
Example: Take the address 0x00FF1234. The binary representation of this address is 00000000111111110001001000110100. By splitting this up, we get 0000000011 1111110001 001000110100, or 0x3 0x3F1 0x234. So item 3 in the first level table gives the address of the second level table, item 0x3F1 in the second table gives the address of the page used, and the address is 0x234 bytes into that page.
This blog series has a very indepth set of examples for how the page table works, how to convert virtual<->physical addresses and such.
Here's an exerpt;
It is obvious that the offset takes 12 bits.
When the size of each entry is 4bytes, you get result that 10 bits for outer page table and 10 bits for inner table table. The calculation is as following:
(2^20 entries × 4 bytes/entry)/4k bytes = 2^10 --> outer page table should have 10 bits
(space taken by page table)/frame(or page)size = no. of inner page tables
4k bytes/4 bytes = 2^10 --> inner page table should have 10 bits
(size of pages in page table)/size of entries = no. frames
That how it gets 10 bits and 10 bits evenly. For different situation, it is not necessary to have even distribution.