For the following VHDL Code - vhdl

Question

For the following VHDL code, assume that D changes to '1' at time 5 ns. Give the values of A, B, C, D, E, and F each time a change occurs. That is, give the values at time 5 ns, 5 + delta, 5 + 2(delta), etc. Carry this out until either 20 steps have occurred, until no further change occurs, or until a repetitive pattern emerges.
entity prob4 is
port (D: inout bit);
end prob4;
architecture q1 of prob4 is
signal A,B,C,E,F: bit;
begin
C <= A;
A <= (B and not E) or D;
P1: proecess (A)
begin
B <= A;
end prcoess P1;
P2: process
wait until A <= '1';
wait for 0 ns;
E <= B after 5 ns;
D < = '0';
F <= E;
end process P2;
end architecture q1;

Answer 1

The problem as presented
There are some obvious syntax errors:
entity prob4 is
port (D: inout bit);
end prob4;
architecture q1 of prob4 is
signal A,B,C,E,F: bit;
begin
C <= A;
A <= (B and not E) or D;
P1: proecess (A) -- misspelled process
begin
B <= A;
end prcoess P1; -- misspelled process
P2: process
-- begin -- missing begin
wait until A <= '1';
wait for 0 ns;
E <= B after 5 ns;
D < = '0'; -- should be "<=" (a single delimiter token signifying assignment)
F <= E;
end process P2;
end architecture q1;
Answering this problem appears to require you've paid attention to lectures, taken notes and/or done the required reading.
Note that there are two drivers one in process P2 assigning D, the other the mode inout port D. There is no resolution for type BIT, implying some event not shown by the VHDL design specification is responsible for D to be assigned a value of 1 at 5 ns and that actual for port D isn't driven. A resolution function can be associated with any subtype declaration (and a port declaration declares a subtype).
That isn't the case here:
entity tb_prob4 is
end entity;
architecture foo of tb_prob4 is
signal D: bit;
begin
DUT:
entity work.prob4 port map (D);
STIMULUS:
process
begin
D <= '1' after 5 ns;
wait;
end process;
end architecture;
ghdl -a prob4 .vhdl
ghdl -e tb_prob4
ghdl -r tb_prob4
./tb_prob4:error: several sources for unresolved signal
for signal: .tb_prob4(foo).ghdl: compilation error
You could theoretically answer the 'problem' supplied in your 'question' by stepping the simulation of an analyzed version of prob4 with the appropriate VHDL tool. This would require forcing D to '1' at 5 ns and releasing it in the next delta cycle (after a step) in the device under test. Otherwise it's a nonsense problem, the VHDL design specification is invalid (see above). You could surmise the bit about "assume that D changes to '1'" was added to stave off questions about the validity.
Solving the problem
The problem can also also be done by hand (paper and pencil).
"... assume that D changes to '1' at time 5 ns" sounds like it implies a single event (no lasting force).
In VHDL an uninitialized signal will take the left most value, which for an enumerated value of type bit is '0' (See package std.standard). This tells you what everything is up to 5 ns. (What's the initial value of A,B,C,D,E,F ?)
Delta cycles are inferred by assignment to the current simulation time. Simulation time advances when further signal assignments are scheduled for the current simulation time. Simulation time is then advanced to the next time a scheduled transaction is present in a projected output waveform for the modeled design hierarchy.
An after schedules a signal event in the projected output waveform for it's target. In the example that would be the current value of B that is scheduled to be assigned to D.
Simulation time advances to the next time with an event (wait, after), wait for 0 ns refers to the current simulation time, will that cause a delta cycle?