VHDL Generic delay - test bench and config - vhdl

Question

I have been modelling a few simple VHDL gates, but I can't seem to get the time delay rightI have the following code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY AND_4 IS
GENERIC (delay : delay_length := 0 ns);
PORT (a, b, c, d : IN std_logic;
x : OUT STD_logic);
END ENTITY AND_4;
ARCHITECTURE dflow OF AND_4 IS
BEGIN
x <= ( a and b and c and d) AFTER delay;
END ARCHITECTURE dflow;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY TEST_AND_4 IS
END ENTITY TEST_AND_4;
ARCHITECTURE IO OF TEST_AND_4 IS
COMPONENT AND_4 IS
GENERIC (delay : delay_length := 0 ns);
PORT (a, b, c, d : IN std_logic;
x : OUT STD_logic);
END COMPONENT AND_4;
SIGNAL a,b,c,d,x : std_logic := '0';
BEGIN
G1 : AND_4 GENERIC MAP (delay => 5ns) PORT MAP (a,b,c,d,x);
PROCESS
VARIABLE error_count : integer:= 0;
BEGIN
WAIT FOR 1 NS;
a <= '1';
b <= '0';
c <= '0';
d <= '0';
ASSERT (x = '1') REPORT "output error" SEVERITY error;
IF (x /= '1') THEN
error_count := error_count + 1;
END IF;
--Repeated test vector -- omitted
END PROCESS;
END ARCHITECTURE IO;
CONFIGURATION TESTER1 OF TEST_AND_4 IS
FOR IO
FOR G1 : AND_4
USE ENTITY work.AND_4(dflow)
GENERIC MAP (delay);
END FOR;
END FOR;
END CONFIGURATION TESTER1;
When I simulate the model I only get the 1 ns delay that I added to each test vector. I'm guessing the problem is how I pass the delay to the component declaration in the test bench. I've tried a few things and reread the topic in the book I have but still no joy. Any help ?
Many thanks
D

Answer 1

modifying the unlabelled stimulus process in your testbench:
process
variable error_count : integer:= 0;
begin
wait for 1 ns;
a <= '1';
-- b <= '0';
-- c <= '0';
-- d <= '0';
-- assert (x = '1') report "output error" severity error;
-- if (x /= '1') then
-- error_count := error_count + 1;
-- end if;
--repeated test vector -- omitted
b <= '1';
c <= '1';
d <= '1';
wait for 5 ns;
wait for 5 ns;
wait;
end process;
to simply demonstrated the delay shows that the generic delay is being passed to the instantiated component:
If you get something different perhaps you could convert your question to a Minimal, Complete, and Verifiable example by ensuring that the example actually reproduces the problem and that we know your results:
Describe the problem. "It doesn't work" is not a problem statement. Tell us what the expected behavior should be. Tell us what the exact wording of the error message is, and which line of code is producing it. Put a brief summary of the problem in the title of your question.
The little bit of stimulus you left in your testbench doesn't appear properly test the and_4.
In the event there was more stimulus and you weren't waiting the pulse rejection limit implied by your signal assignment delay mechanism, you'd get nothing but those annoying assertions.
See IEEE Std 1076-2008 10.5. Simple signal assignment statements, 5.2.1 General, paragraphs 5 and 6:
The right-hand side of a simple waveform assignment may optionally specify a delay mechanism. A delay mechanism consisting of the reserved word transport specifies that the delay associated with the first waveform element is to be construed as transport delay. Transport delay is characteristic of hardware devices (such as transmission lines) that exhibit nearly infinite frequency response: any pulse is transmitted, no matter how short its duration. If no delay mechanism is present, or if a delay mechanism including the reserved word inertial is present, the delay is construed to be inertial delay. Inertial delay is characteristic of switching circuits: a pulse whose duration is shorter than the switching time of the circuit will not be transmitted, or in the case that a pulse rejection limit is specified, a pulse whose duration is shorter than that limit will not be transmitted.
Every inertially delayed signal assignment has a pulse rejection limit. If the delay mechanism specifies inertial delay, and if the reserved word reject followed by a time expression is present, then the time expression specifies the pulse rejection limit. In all other cases, the pulse rejection limit is specified by the time expression associated with the first waveform element.
(Note you can go to 10.5.2.2 Executing a simple assignment statement and see the after time_expression is part of the waveform_element and not the delay mechanism).

Answer 2

Sure
ENTITY TEST_AND_4 IS
END ENTITY TEST_AND_4;
ARCHITECTURE IO OF TEST_AND_4 IS
COMPONENT AND_4 IS
GENERIC (delay : delay_length := 0 ns);
PORT (a, b, c, d : IN std_logic;
x : OUT STD_logic);
END COMPONENT AND_4;
SIGNAL a,b,c,d,x : std_logic := '0';
BEGIN
G1 : AND_4 GENERIC MAP (delay => 5 NS) PORT MAP (a,b,c,d,x);
PROCESS
VARIABLE error_count : integer:= 0;
BEGIN
WAIT FOR 1 NS; -- Changed to 6 ns so that the wait is longer then the
-- generic gate propagation delay
a <= '1';
b <= '1';
c <= '1';
d <= '1';
ASSERT (x = '1') REPORT "output error" SEVERITY error;
IF (x /= '1') THEN
error_count := error_count + 1;
END IF;
I have noted the change I made to the test bench model above, seems kinda obvious now but yesterday it had me pulling my hair out.
Cheers
D
The 'fix' was to change the WAIT value in the sequential test bench model from 1 ns to 6 ns. This gives the gate the time to change state because it has a 5 ns inertial delay.
WAIT FOR 6 NS; -- Changed to 6 ns so that the wait is longer then the
-- generic gate propagation delay

Answer 3

Thanks for the help, but I spotted the problem this morning after reading USER115520's post. The delay I set was 'inertial' and set generically at 5 ns. In my test bench process I had only set 1 ns wait statements in between input signal changes. Thus the gate would not perform the transition when the correct stimuli and introduced.
I inserted a 6 ns delay after a=1 b=1 c=1 d=1 and got the correct response from the gate