Is it possible to define looping functions in a test bench - vhdl

Question

I am doing a past paper in preparation for an exam and one of the questions shows this waveform:
Now I know of course that you could just write the code out line by line like so:
sig1 <= '1'; sig2 <= '1'; y <= '1'; wait for 20 ns;
y <= '0'; wait for 5 ns;
-- etc.
or by utilising arrays. I was wondering if it was possible to streamline the process by setting up looping functions that can be called and run simultaneously.
-- Some pseudocode
function sig1 is
sig1 <= '1'; wait for 25 ns;
sig1 <= '0'; wait for 50 ns;
end sig1;
-- Definition for the other waves goes here
function waveform is
while n=1 loop
sig1, sig2, y run;
end loop;
end waveform;
I've already had a poke around the documentation for VHDL and here on Stack Overflow but I must apologise in advance, I haven't a clue as to what you would call something like this so my searches haven't yielded any results close to what I am thinking. This is just a curiosity of course, I already expect that because of the nature of the hardware and language in question it just might not be possible.
Thank you though in advance for any help!

Answer 1

VHDL for test bench can be more software like, since it does not need to be synthesizable.
The ´y´ part can be written with loop as shown below, and the other parts can be made in a similar fashion.
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end entity;
architecture sim of tb is
signal y : std_logic;
begin
process is
constant period : time := 80 ns;
constant steps : natural := 8;
begin
for i in 0 to steps - 1 loop
case i is
when 0 | 1 | 3 => y <= '1';
when others => y <= '0';
end case;
wait for period / steps;
end loop;
end process;
end architecture;
The above makes use of the VHDL feature, that a process without sensitivity list will restart when the end is reached.
Waveform will be:

Answer 2

VHDL signal assignment allows for waveforms with multiple elements:
IEEE Std 1076-2008
10.5.2 Simple signal assignments
10.5.2.1 General
simple_signal_assignment ::=
simple_waveform_assignment
| simple_force_assignment
| simple_release_assignment
simple_waveform_assignment ::=
target <= [ delay_mechanism ] waveform ;
delay_mechanism ::=
transport
| [ reject time_expression ] inertial
target ::=
name
| aggregate
waveform ::=
waveform_element { , waveform_element }
| unaffected
10.5.2.2 Executing a simple assignment statement
waveform_element ::=
value_expression [ after time_expression ]
| null [ after time_expression ]
Evaluation of a waveform element produces a single transaction. The time component of the transaction is determined by the current time added to the value of the time expression in the waveform element. For the first form of waveform element, the value component of the transaction is determined by the value expression in the waveform element. For the second form of waveform element, the value component is not defined by the language, but it is defined to be of the type of the target. A transaction produced by the evaluation of the second form of waveform element is called a null transaction.
This emulates waveform descriptions found in pattern generators for test languages and IC testers. Multiple waveform elements are intended for simulation typically in testbenches and are not supported by synthesis.
The projected output waveform is a queue of waveform elements that must occur in ascending time order.
Also process statements inherently loop:
11.3 Process statement
The execution of a process statement consists of the repetitive execution of its sequence of statements. After the last statement in the sequence of statements of a process statement is executed, execution will immediately continue with the first statement in the sequence of statements.
These two features allow writing compact independent pattern generators in testbenches:
library ieee;
use ieee.std_logic_1164.all;
entity sig1sig2y_tb is
end entity;
architecture foo of sig1sig2y_tb is
signal sig1, sig2, y: std_ulogic;
begin
sig1_process:
process
begin
sig1 <= '1', '0' after 25 ns;
wait for 75 ns;
end process;
sig2_process:
process
begin
sig2 <= '1', '0' after 25 ns, '1' after 75 ns, '0' after 100 ns,
'1' after 125 ns, '0' after 175 ns;
wait for 200 ns;
end process;
y_process:
process
begin
y <= '1', '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
wait for 80 ns;
end process;
end architecture;
Note the waveform element delay is relative to the current simulation time.
This testbench produces the target waveforms: