Generating a generic delay package in VHDL - vhdl

Question

I'm looking for the correct syntax to build a generic line delay package using generics and for loops in a process. I understand that for loops when used with generate are for concurrent statements, but surely there must be a way to build it.
For example:
entity Delay_Line is
Generic (
CLK_DELAYS : integer := 10);
Port (
CLK : in STD_LOGIC;
i_Din : in STD_LOGIC;
o_Q : out STD_LOGIC;
o_Qnot : out STD_LOGIC);
end Delay_Line;
architecture Delay_Line_arch of Delay_Line is
signal din_dly : std_logic_vector(CLK_DELAYS-1 downto 0);
begin
din_dly(0) <= i_Din;
process(CLK)
begin
if rising_edge(CLK) then
for index in 0 to CLK_DELAYS-1 generate
begin
din_dly(index+1) <= din_dly(index);
end;
end if;
end process;
o_Q <= din_dly(CLK_DELAYS);
o_Qnot <= NOT (din_dly(CLK_DELAYS));
end Delay_Line_arch;
Typically I would just add a bunch of:
din_delay(9) <= din_delay(8);
din_delay(8) <= din_delay(7);
...
in the code, but honestly I'd like something a little more reusable as a package.

Answer 1

It isn't really necessary to use such elaborate methods to implement shift registers. You can implement them directly in one line using array concatenation and slicing.
constant DELAY_STAGES : positive := 10; -- Or use a generic parameter
signal delay_line : std_logic_vector(1 to DELAY_STAGES);
...
process(clk) is
begin
if rising_edge(clk) then
delay_line <= i_Din & delay_line(1 to DELAY_STAGES-1); -- Shift right
end if;
end process;
-- Retrieve the end of the delay without a hard-coded index
o_Q <= delay_line(delay_line'high);
The brevity of this approach pretty much eliminates any convenience of having a component that you need to instantiate with port and generic maps. Plus you have the flexibility of being able to tap off whatever intermediate signals you may need.

Answer 2

Well I don’t have 50 rep yet but to get Pablo R’s method to work with large busses and delays bus_size := 16 and delay := 256. I had to change:
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);
to
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (bus_size);

Answer 3

A bit late, but this is my generic_delay component:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY generic_delay is
generic (
bus_size : natural;
delay : natural
);
port (
i_Clock : IN STD_LOGIC;
i_reset : IN STD_LOGIC;
i_bus1 : in std_logic_vector(bus_size - 1 downto 0);
i_bus2 : in std_logic_vector(bus_size - 1 downto 0);
o_bus1 : out std_logic_vector(bus_size - 1 downto 0);
o_bus2 : out std_logic_vector(bus_size - 1 downto 0)
);
end generic_delay;
architecture a of generic_delay is
----------------------------
-- SIGNALS DECLARATION
----------------------------
signal temp_bus1 : std_logic_vector(delay*bus_size - 1 downto 0);
signal temp_bus2 : std_logic_vector(delay*bus_size - 1 downto 0);
BEGIN
-----------------------------------------
-- SYNCHRONOUS PROCESS
-----------------------------------------
process(i_Clock, i_reset)
begin
if i_reset = '1' then
temp_bus1 <= (others => '0');
temp_bus2 <= (others => '0');
elsif falling_edge(i_Clock) then
if delay > 1 then
temp_bus1 <= i_bus1 & temp_bus1(delay*bus_size - 1 downto (delay-1)*bus_size);
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);
else
temp_bus1 <= i_bus1;
temp_bus2 <= i_bus2;
end if;
elsif (RISING_EDGE(i_Clock)) then
o_bus1 <= temp_bus1(bus_size - 1 downto 0);
o_bus2 <= temp_bus2(bus_size - 1 downto 0);
end if; -- reset + rising_edge(clk)
end process logic;
-------------------------------------------------------
end a;