How can I implement Division and Multiplication manually in VHDL? That is; using Left & Right Shift and without the need for numeric_std (If possible).
A possible soulution:
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Shifter is
generic(
num_length : integer := 32
);
port(
EN : in std_logic;
clk : in std_logic;
number : in std_logic_vector((num_length - 1) downto 0);
dir : in std_logic;
result : out std_logic_vector((num_length - 1) downto 0));
end Shifter;
architecture Beh of Shifter is
signal temp : std_logic_vector((num_length - 1) downto 0);
begin
result <= std_logic_vector(temp);
process(EN, clk) is
begin
if EN = '0' then
temp <= (OTHERS => '0');
elsif rising_edge(clk) then
case dir is
when '0' => temp <= '0' & number((num_length - 2) downto 0);
when '1' => temp <= number((num_length - 2) downto 0) & '0';
end case;
end if;
end process;
end Beh;
Every clk cycle the position increases/decreases (depends on dir setting)
It can also be released with loops so that the module can increase/decrease more than one bit at a cycle.
Important: It is only possible to increase/decrease by the power of 2 (2,4,8,16,32,...) with shifting
Related
I've been asked at the university to make a 4-bit bidirectional shift register. I did it first this way:
-- bidirektionale shift register mit data-load und serielle(R/L) output
library ieee;
use ieee.std_logic_1164.all;
entity bi_shift_reg is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Serial Shift-Right output
s_dout_L: out std_logic -- Serial Shift-Left output
);
end bi_shift_reg;
architecture arch of bi_shift_reg is
begin
process(clk,set,n_reset)
begin
-- reset (low aktiv)
if n_reset = '0' then dout <= "0000";
-- set
elsif set = '1' then dout <= "1111";
-- data-load
elsif(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
dout <= din;
-- shift right
elsif(rising_edge(clk) and sR = '1') then
s_dout_R <= din(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
s_dout_L <= din(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end process;
end arch;
but then I heard that I needed to use my previous coded D-Flipflop as a component for the shift register. So my question is: since I have new inputs (data_load,shift_left and shift_right) and outputs(Serial Shift-Right, Serial Shift-Left) how can I add them in my code along with the d-ff component? is it possible to use a component and process together ?
This is my d-ff code with asynchronous activ-low reset and asynchronous set:
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk,set,n_reset)
variable temp: std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
How can I use my flipflop to achieve the same result as the code for the shift-register ?
Thank you in advance for your answers :D
After several good questions in the comment track by the OP, it is reasonable to post some design that can serve as an example for a solution.
Please note, that there was not any precise specification of the intended operation, e.g. what is priority between different inputs, and how should timing be for outputs, so the code below is provided with the intention of showing some VHDL structures that may works as a template for further update by the OP.
--###############################################################################
-- d_flipflop
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk, set, n_reset)
variable temp : std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
--###############################################################################
-- bi_shiftReg_ff
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port(din : in std_logic_vector(3 downto 0);
set, n_reset : in std_logic;
sR, sL : in std_logic; -- Shift-Right/Shift-Left
data_load : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(3 downto 0);
s_dout_R : out std_logic; -- Shift-Right output
s_dout_L : out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
-- FF component
component d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end component;
-- FF data input
signal d : std_logic_vector(3 downto 0);
-- FF data output
signal q : std_logic_vector(3 downto 0);
signal qn : std_logic_vector(3 downto 0); -- Unused, but included for completness
begin
-- Combinatorial process, thus making gates only
process (all)
begin
-- data-load
if (data_load = '1') then
d <= din;
-- shift right; priority over shift left
elsif (sR = '1') then
d <= '0' & q(q'left downto 1); -- Discard right-most bit in the right shift
-- shift left
elsif (sL = '1') then
d <= q(q'left - 1 downto 0) & '0'; -- Discard left-most bit in the left shift
end if;
end process;
-- State held in FFs
GEN_REG : for i in 0 to 3 generate
REGX : d_flipflop port map
(d(i), clk, set, n_reset, q(i), qn(i));
end generate;
-- Outputs drive
dout <= q;
s_dout_R <= q(q'right); -- Bit 0, but shown with VHDL attributes
s_dout_L <= q(q'left); -- Bit 3, --||--
end arch;
--###############################################################################
-- EOF
So I've been working on some homework for my VHDL course and I can't seem to understand this problem.
The point here is to create the adder/subtractor of an ALU that works both on 2's complement and unsigned 32-bit buses, which is why I have a condition called sub_mode ( A - B = A + !B + 1 ) which will also be the carry-in when activated.
The rest of the different inputs and outputs are pretty self-explanatory.
My problem is with the testbenching of such component where, even though carry_temp and r_temp have been initialized in declaration section of the architecture, end up showing up undefined. I have guessed that it is due to the for loop within the process screwing everything up. Would that be an accurate guess? And if yes, is it possible to proceed to add two bit buses together without having to fully create an n-bit adder made from n 1-bit adder components?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_sub is
port(
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
sub_mode : in std_logic;
carry : out std_logic;
zero : out std_logic;
r : out std_logic_vector(31 downto 0)
);
end add_sub;
architecture synth of add_sub is
signal cond_inv : std_logic_vector(31 downto 0);
signal carry_temp : std_logic_vector(32 downto 0) := (others => '0');
signal r_temp : std_logic_vector(31 downto 0) := (others => '0');
begin
behave : process(a,b,sub_mode)
begin
if sub_mode = '1' then
cond_inv <= b xor x"ffffffff";
else
cond_inv <= b;
end if;
carry_temp(0) <= sub_mode;
for i in 0 to 31 loop
r_temp(i) <= a(i) xor cond_inv(i) xor carry_temp(i);
carry_temp(i+1) <=
(a(i) and cond_inv(i)) or
(a(i) and carry_temp(i)) or
(cond_inv(i)and carry_temp(i));
end loop;
if r_temp = x"00000000" then
zero <= '1';
else
zero <= '0';
end if;
r <= r_temp;
carry <= carry_temp(32);
end process behave;
end synth;
I am trying to make set&load d-flip flop code(synch) but it keeps giving me count <= '0' & d; it has 2 elements but must have 9 elements error.Thanks in advance
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity syn is
port (
clk : in std_logic;
rst_n : in std_logic;
d : in std_logic;
ld : in std_logic;
q : out std_logic_vector(7 downto 0);
co : out std_logic);
end syn;
architecture rtl of syn is
signal count : std_logic_vector(8 downto 0);
begin
co <= count(8);
q <= count(7 downto 0);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_n = '0') then
count <= (others => '0'); -- sync reset
elsif (ld = '1') then
count <= '0' & d; -- sync load
else
count <= count + 1; -- sync increment
end if;
end if;
end process;
end rtl;
Input d is std_logic, so '0' & d is 2 bit vector. Count is std_logic_vector of length 9, so you can't make assignment like this.
I'm not entirely sure what you are trying to achieve. If you want to assign '0' & d to some part of a vector, you can write for example
count(1 downto 0) <= '0' & d
If d is supposed to be equal size of counter, then change it's size in entity declaration.
I am rather new (3 weeks) to VHDL, and I am having a problem in my latest assignment, which involves implementing overflow checking in a simple 4-bit adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_sub_4bit is
Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
b : inout STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC );
--sum : inout STD_LOGIC_VECTOR(3 downto 0)
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal localsum : STD_LOGIC_VECTOR (3 downto 0);
begin
localsum <= a + b when sel = '1'
else
a - b;
process(a,b,localsum) begin
if a(3) = '0' AND b(3) = '0' AND localsum(3) = '1' then
localflow <= '1';
elsif a(3) = '1' AND b(3) = '1' AND localsum(3) = '0' then
localflow <='1';
else
localflow <='0';
end if;
end process;
end Behavioral;
Now, the test cases are as such:
A=5, B=-3, giving 0 to sel adds them, 1 subtracts.
A=6, B=2, working much the same.
Now, given that the numbers are signed, of course, they are two's complement numbers, so is the result. However, I can only detect overflow in a case of adding 6 (0110) and 2 (0010), giving out -8 (1000), which is obviously an overflow case in 4-bit. But, when doing 5 -(-3), the result is much the same, 1000, but since I have given numbers of two different signs, I cannot detect overflow using my method.
My teacher has suggested that we change the sign of B depending on the value of sel - I tried something like making b <= b+"1000" based on that but that didn't help, and I don't know of other ways, being very new to the language. What can I do to get a proper program? Thank you.
Firstly:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Don't do that. Especially if you want the numbers to be signed. Normal to use is:
use IEEE.numeric_std.all;
After that, you should cast the std_logic_vector to the wanted data type, e.g. 'signed', for the correct arithmetic.
Secondly, don't use inout. VHDL is not so good with bidirectional assignments. Either use in or out.
So combining the above, you could do (n.b. not the best code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
overflow : out std_logic
);
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal locala, localb, localsum : signed(4 downto 0); -- one bit more then input
signal sumout : std_logic_vector(4 downto 0);
begin
locala <= resize(signed(a), 5);
localb <= resize(signed(b), 5);
localsum <= locala + localb when sel = '1' else locala - localb;
-- overflow occurs when bit 3 is not equal to the sign bit(4)
localflow <= '1' when localsum(3) /= localsum(4) else '0';
-- convert outputs
sumout <= std_logic_vector(localsum);
--outputs
sum <= sumout(4)&sumout(2 downto 0);
overflow <= localflow;
end Behavioral;
You can test this using a testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit_tb is
end add_sub_4bit_tb;
architecture Behavioral of add_sub_4bit_tb is
signal sel : std_logic_vector(0 downto 0);
signal a, b, sum : std_logic_vector(3 downto 0);
begin
uut: entity work.add_sub_4bit
port map (a, b, sel(0), sum);
test: process
begin
for sel_o in 0 to 1 loop
sel <= std_logic_vector(to_signed(sel_o, 1));
for a_o in -8 to 7 loop
a <= std_logic_vector(to_signed(a_o, 4));
for b_o in -8 to 7 loop
b <= std_logic_vector(to_signed(b_o, 4));
wait for 1 ns;
end loop;
end loop;
end loop;
wait;
end process;
end Behavioral;
I'm trying to make a VHDL code for 4-bit universal shift register, where I want to load 4 bits and choose the shift-operation from the ctrl. I don't know how to implement a clock divider to run the outputs on a FPGA.
Here is my code so far:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity shift_register is
generic(N : integer := 4);
port(
clk, reset : in std_logic;
ctrl : in std_logic_vector(1 downto 0);
d : in std_logic_vector((N-1) downto 0);
q : out std_logic_vector((N-1) downto 0)
);
end shift_register;
architecture Behavioral of shift_register is
signal r_reg : std_logic_vector((N-1) downto 0);
signal r_next : std_logic_vector((N-1) downto 0);
begin
process(clk, reset)
begin
if(reset = '1') then
r_reg <= (others => '0');
elsif(clk'event and clk = '1') then
r_reg <= r_next;
end if;
end process;
with ctrl select
r_next <=
r_reg when "00", --do nothing
r_reg(N-2 downto 0) & d(0) when "01", --shift left
d(N-1) & r_reg(N-1 downto 1)when "10", --shift right
d when others; --load
q <= r_reg;
end Behavioral;
Divider code template with enable asserted a single cycle every RATIO clock cycles:
library ieee;
use ieee.numeric_std.all;
architecture syn of mdl is
constant RATIO : natural := 10;
signal prescale : std_logic_vector(9 downto 0); -- Scale to fit RATIO - 1
signal enable : std_logic;
begin
process (clk, reset) is
begin
if reset = '1' then
enable <= '0';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
elsif rising_edge(clk) then
if unsigned(prescale) = 0 then
enable <= '1';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
else
enable <= '0';
prescale <= std_logic_vector(unsigned(prescale) - 1);
end if;
end if;
end process;
end architecture;