I have a 12 bits vector called RDIBits and a in std_logic called InUartToUart. My question is: every time the clock goes to '1', i receive a bit in InUartToUart, and i want to concat all the 12 bits that i will receive in the RDIBits vector. Basically, its a serial communication, thats why i receive 1 bit each time. Is there any simple way to do this? Something similar to RDIBits += InUartToUart in JAVA.
I would code this slightly differently. Maybe consider this.
Sorry about the formatting, Im new to this site. I have also shown how you can initialise the variable.
signal RDIBits : std_logic_vector(11 downto 0) := (Others => '0');
...
process(clk)
begin
if ( rising_edge(clk) ) then
RDIBits(11 downto 1) <= RDIBits(10 downto 0);
RDIBits(0) <= InUartToUart;
end if;
end process;
I added some more things, like the entity, the IOs and a counter for the output register.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY my_uart IS
PORT(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- reset high active
---------------------------------------------
InUartToUart : IN std_logic;
DataOut : OUT std_logic_vector(11 downto 0)
);
END ENTITY;
ARCHITECTURE struct OF my_uart IS
signal RDIBits : std_logic_vector(11 downto 0);
signal counter : integer range 0 to 12;
begin
calc_proc: process(clk, rst)
begin
if (rst = '1') then
RDIBits <= (others => '0');
counter <= 0;
elsif ( rising_edge(clk) ) then
if (counter < 12) then
RDIBits <= RDIBits(10 downto 0) & InUartToUart;
counter <= counter + 1;
elsif (counter = 12) then
DataOut <= RDIBits;
counter <= 0;
end if;
end if;
end process;
END STRUCT;
This is a typical shift register application. For example:
signal RDIBits : std_logic_vector(11 downto 0);
...
process(clk)
begin
if ( rising_edge(clk) ) then
RDIBits <= RDIBits(10 downto 0) & InUartToUart;
end if;
end process;
Related
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity struture_test is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Init : in STD_LOGIC;
i_ia : in STD_LOGIC_VECTOR (11 downto 0);
i_ib : in STD_LOGIC_VECTOR (11 downto 0);
end_s : out std_logic;
result : out STD_LOGIC_VECTOR (11 downto 0));
end struture_test;
architecture Behavioral of struture_test is
signal en_sn : std_logic := '0';
begin
PROCESS (clk,rst)
variable acc : signed (23 downto 0) ;
variable x : signed (35 downto 0) ;
begin
if (rst = '0') then
result <= (others => '0');
end_s <= '0';
elsif (rising_edge (clk)) then
if ((Init) = '1') then
acc := signed (i_ia)*signed (i_ib);
x := acc * signed (i_ia);
result <= std_logic_vector (x(23 downto 12));
end_s <= '1';
else
end_s <= '0';
end if;
end if;
end process;
end Behavioral;
Hi everyone
I have a project which includes some blocks. The blocks link each other through Init or End Signal. It means that The End signal of one Block is connected to Init signal of the following block.
I'm confused about that Does the above code make a good Init and a End signal ?
If I change my code and convert it into Pipelined structure to operate with the higher frequency clock. The variables convert into the signals
PROCESS (clk,rst)
signal acc : signed (23 downto 0) ;
signal x : signed (35 downto 0) ;
begin
if (rst = '0') then
result <= (others => '0');
end_s <= '0';
elsif (rising_edge (clk)) then
if ((Init) = '1') then
acc <= signed (i_ia)*signed (i_ib);
x <= acc * signed (i_ia);
result <= std_logic_vector (x(23 downto 12));
end_s <= '1';
else
end_s <= '0';
end if;
end if;
end process;
How to create Init and End signal in this case? The block illustrates in the picture
The idea is good, but the code is wrong. In addition it has some bad coding smells.
Basic rules:
Do not use asynchronous resets.
You can not declare signals in processes. Process allow variable declarations; architectures allow signal declarations.
Each signal assignment in a clock process creates a flip-flop / delay of one clock cycle. So it's 3 clock cycles delay in total, but you end signal is only delayed by one cycle.
Do not enable pipelined operations. Use a delayed chain of valid bits.
Do not reset pipeline results, because underlying hardware resources like DSP (multiplication) units do not support resets.
Changed code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity struture_test is
port (
clk : in std_logic;
rst : in std_logic;
Init : in std_logic;
i_ia : in std_logic_vector(11 downto 0);
i_ib : in std_logic_vector(11 downto 0);
end_s : out std_logic;
result : out std_logic_vector(11 downto 0) := (others => '0');
);
end entity;
architecture rtl of struture_test is
signal ValidChain : std_logic_value(2 downto 0) := (others => '0');
signal ia_delayed : signed(i_ia'range) := (others => '0');
signal acc : signed(23 downto 0) := (others => '0');
signal x : signed(35 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
ValidChain <= ValidChain(ValidChain'high - 1 downto ValidChain'low) & Init;
acc <= signed(i_ia) * signed(i_ib);
ia_delayed <= signed(i_ia);
x <= acc * ia_delayed;
result <= std_logic_vector(x(23 downto 12));
end if;
end process;
end_s <= ValidChain(ValidChain'high);
end architecture;
Please note: Signal i_ia used in the 2nd multiplication needs to be delayed by one cycle, otherwise you would mix ia values from different pipeline cycles.
I am doing a project in college and want to produce a triangular wave using a DAC2904 and a Spartan 3 xc3s5000 board.
I have written code for it but is not working.
I don't know may be it is the problem in code or in my ucf file:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity traingular is
Port (
clk : in std_logic; -- on board clock
reset : in std_logic;
dac_clk : out std_logic; -- clk for dac module
output : out std_logic_vector(13 downto 0); -- output to dac
wr_dac : out std_logic -- pulse given to write pin of dac ic.
);
end traingular;
architecture Behavioral of traingular is
signal counter : unsigned(3 downto 0);
signal divide : std_logic_vector(15 downto 0);
signal sampling_clk , clk_s : std_logic;
signal decade : std_logic_vector(3 downto 0);
-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much
begin
process(clk, reset)
begin
if (reset = '1' ) then
decade <= (others => '0');
elsif (clk' event and clk = '1') then
if (decade = "1010") then
decade <= (others => '0');
else
decade <= std_logic_vector(unsigned(decade) + 1);
end if;
end if;
end process;
clk_s <= '1' when decade = "1010" else
'0';
process(clk_s , reset)
begin
if (reset='1') then
divide <= (others => '0');
elsif (clk_s'event and clk_s = '1') then
divide <= std_logic_vector(unsigned(divide) + 1);
end if;
end process;
sampling_clk <= divide(2);
-- input click is still fast so clock is divided further
dac_clk <= sampling_clk;
wr_dac <= sampling_clk;
process(clk , reset)
begin
-- code below is for counter which will further feed to dac to produce traingular wave.
if (reset = '1' ) then
counter <= (others => '0');
elsif (clk' event and clk = '1') then
if (counter = "1010") then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
output <= "0000000000" & std_logic_vector(counter); -- output to dac.
end Behavioral;
So, can you guys tell me what is the problem in my code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tri_wave is
Port ( clk : in STD_LOGIC;
rst :in STD_LOGIC;
up_step_size,down_step_size:in std_logic_vector(2 downto 0);
dac_out : out STD_LOGIC_VECTOR (7 downto 0));
end tri_wave;
architecture Behavioral of tri_wave is
signal dac_wav:std_logic_vector(7 downto 0);
signal count:std_logic_vector(7 downto 0);
signal dir:std_logic:='0';
begin
process(clk,rst,dir)
begin
if rst='1' then
count<=(others=>'0');
elsif dir='0' then
if clk'event and clk='1' then
if count="01111111" then
dir<='1' ;
else
count<= count + up_step_size;
end if;
end if;
elsif dir='1' then
if clk'event and clk='1' then
if count="10000000" then
dir<='0' ;
else
count<= count - down_step_size;
end if;
end if;
end if;
end process;
--dac_out<=count;
dac_out<=count(count'high) & count(6 downto 0);
end Behavioral;
i think this code gives u better idea just creaet tb and simulae i odelsim u will get it.
I'm trying to make a VHDL code for 4-bit universal shift register, where I want to load 4 bits and choose the shift-operation from the ctrl. I don't know how to implement a clock divider to run the outputs on a FPGA.
Here is my code so far:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity shift_register is
generic(N : integer := 4);
port(
clk, reset : in std_logic;
ctrl : in std_logic_vector(1 downto 0);
d : in std_logic_vector((N-1) downto 0);
q : out std_logic_vector((N-1) downto 0)
);
end shift_register;
architecture Behavioral of shift_register is
signal r_reg : std_logic_vector((N-1) downto 0);
signal r_next : std_logic_vector((N-1) downto 0);
begin
process(clk, reset)
begin
if(reset = '1') then
r_reg <= (others => '0');
elsif(clk'event and clk = '1') then
r_reg <= r_next;
end if;
end process;
with ctrl select
r_next <=
r_reg when "00", --do nothing
r_reg(N-2 downto 0) & d(0) when "01", --shift left
d(N-1) & r_reg(N-1 downto 1)when "10", --shift right
d when others; --load
q <= r_reg;
end Behavioral;
Divider code template with enable asserted a single cycle every RATIO clock cycles:
library ieee;
use ieee.numeric_std.all;
architecture syn of mdl is
constant RATIO : natural := 10;
signal prescale : std_logic_vector(9 downto 0); -- Scale to fit RATIO - 1
signal enable : std_logic;
begin
process (clk, reset) is
begin
if reset = '1' then
enable <= '0';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
elsif rising_edge(clk) then
if unsigned(prescale) = 0 then
enable <= '1';
prescale <= std_logic_vector(to_unsigned(RATIO - 1, prescale'length));
else
enable <= '0';
prescale <= std_logic_vector(unsigned(prescale) - 1);
end if;
end if;
end process;
end architecture;
I want to implement a random-number game on BASYS2. In this game there would be five LEDs chosen out of which one would turn on at random for a second or two (this time can be changed to increase or decrease the difficulty level of the game). Then the user is required to respond to this LED event by pressing the switch button behind it within the time that it is on. If he or she is able to do so successfully a point would be scored and it would be showed on the Seven Segment Display. If he or she fails no point would be scored. There would be 9 such events after which the game can be replayed.
Now following is my code (only for the random LED turning on). However, I am unable to fix it. Please somebody help. The FPGA I am using is BASYS2 SPARTAN 3E-100.
Thanks in advance to everyone.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity random_number is
generic ( width : integer := 4 );
port (
clk : in std_logic;
reset : in std_logic;
random_num : out std_logic_vector (width-1 downto 0) --output vector
);
end random_number;
architecture Behavioral of random_number is
signal q: std_logic_vector(23 downto 0);
signal divided_clock: std_logic;
begin
process(clk, reset)
begin
if (reset = '1')then
q <= X"000000";
elsif(rising_edge(clk)) then
q <= q + 1;
end if;
end process;
divided_clock <= q(22);
process (divided_clock)
variable rand_temp : std_logic_vector(width-1 downto 0):=("1000");
variable temp : std_logic := '0';
begin
if(rising_edge(divided_clock)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end Behavioral;
I think the second process should even run with the main clk and the devided clock should be an enable.
signal divided_enable: std_logic;
process(clk, reset)
begin
if (reset = '1')then
q <= X"000000";
elsif(rising_edge(clk)) then
q <= q + 1;
end if;
if (q(22) = '1') then
--short pulse wenn q bit 22 is high
divided_enable <= '1';
q <= (others => '0');
end if;
end process;
process (clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=("1000");
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
if(divided_enable = '1') then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
end if;
random_num <= rand_temp;
end process;
I don't know if this will fix all your problems. Please discribe compiler errors or errors in the behavior.
I have written the following VHDL code which is the component of a Fast Adder. The fast adder consists of an 8by8 register hooked up to adder whose code is below. How can i eliminate the use of inout Read_Adress. I want Read_Adress to be out std_logic_vector not inout?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
Entity Adder is
port(
Clock_50_MHZ :in std_logic;
En :in std_logic;
Data_Registerfile : in std_logic_vector(7 downto 0);
Read_Address: inout std_logic_vector(2 downto 0) := "000";
Output : out std_logic_vector(11 downto 0)
);
end Adder;
Architecture arch of Adder is
Signal result : unsigned (11 downto 0):="000000000000";
Signal regData: std_logic_vector(7 downto 0);
Begin
regData <= Data_Registerfile;
Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ) then
if (En = '1') then
if(Read_Address = "000") then
result <= "000000000000" + unsigned(regData);
Read_Address <= Read_Address + 1;
elsif(Read_Address = "111") then
Output <= std_logic_vector( result + unsigned(regData) );
Read_Address <= "000";
else
result <= result + unsigned(regData);
Read_Address <= Read_Address + 1;
end if;
end if;
end if;
End Process;
end arch;
This is a classic inconvenience in VHDL: you can't use your out ports as
signals (if you are used to Verilog, you often find yourself wanting to do
that).
The best way that I know of is to create an extra dummy signal:
signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";
do the computation with that:
Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ) then
if (En = '1') then
if(Read_Address_tmp = "000") then
result <= "000000000000" + unsigned(regData);
Read_Address_tmp <= Read_Address_tmp + 1;
elsif(Read_Address_tmp = "111") then
Output <= std_logic_vector( result + unsigned(regData) );
Read_Address_tmp <= "000";
else
result <= result + unsigned(regData);
Read_Address_tmp <= Read_Address_tmp + 1;
end if;
end if;
end if;
End Process;
and then link it to your output:
Read_Address <= Read_Address_tmp;
Owen's answer is the usual way, historically.
The "new" VHDL 2008 allows reading of out-mode ports now. If your tools don't support it, log a bug with the vendor. See the bottom of this page from "VHDL 2008 - just the new stuff"
http://books.google.co.uk/books?id=ETxLguPMEY0C&pg=PA163&lpg=PA163#v=onepage&q&f=false