I am using Altera Max plus II, writing in VHDL.
In the architecture I am given this command:
signal count_value : unsigned (3 downto 0);
I noticed that the initial value of count_value is 0000.
How can I change it?
EDIT:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all ;
entity decade_counter is
port ( clk : in std_logic;
q : out unsigned(3 downto 0) );
end entity decade_counter;
architecture rtl of decade_counter is
signal count_value : unsigned(3 downto 0);
begin
count : process (clk) is
begin
if rising_edge(clk) then
if count_value = 9 then
count_value <= "0000";
else
count_value <= count_value + 1;
end if;
end if;
end process count;
q <= count_value;
end architecture rtl;
I have this code which is a BCD Counter from 1 to 9. I want to modify it so that it goes from 7 to 12. That's the reason why I want count_value to initialize at 0111.
Thanks in advance
First - don't use std_logic_arith. It is not part of the standard, and often generates problems. Use numeric_std instead.
Second - initialization. You can do it in two ways:
Init value at declaration of the signal. This is possible, but you must check if your device support it. If you want your code to be portable, use second method.
Reset. Preferably synchronous, as it is usually part of the logic.
Example (haven't checked it, but should work):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ;
entity decade_counter is
port (
clk : in std_logic;
reset_n: in std_logic;
q : out std_logic_vector(3 downto 0)
);
end entity decade_counter;
architecture rtl of decade_counter is
signal count_value : unsigned(3 downto 0);
-- Possibly:
-- signal count_value : unsigned(3 downto 0) := "0111";
begin
count : process (clk) is
begin
if rising_edge(clk) then
if resetn = '0' then
count_value <= "0111";
else
if count_value >= 12 then
count_value <= "0111";
else
count_value <= count_value + 1;
end if;
end if;
end if;
end process count;
q <= std_logic_vector(count_value);
end architecture rtl;
If it be that you want to provide some value to it at build time.I suggest you try this method
signal count_value : unsigned (3 downto 0) := "xxxx";
This "xxxx" could be any std_logic_Vector value you want
Hope it helps!
Related
I have a 12 bits vector called RDIBits and a in std_logic called InUartToUart. My question is: every time the clock goes to '1', i receive a bit in InUartToUart, and i want to concat all the 12 bits that i will receive in the RDIBits vector. Basically, its a serial communication, thats why i receive 1 bit each time. Is there any simple way to do this? Something similar to RDIBits += InUartToUart in JAVA.
I would code this slightly differently. Maybe consider this.
Sorry about the formatting, Im new to this site. I have also shown how you can initialise the variable.
signal RDIBits : std_logic_vector(11 downto 0) := (Others => '0');
...
process(clk)
begin
if ( rising_edge(clk) ) then
RDIBits(11 downto 1) <= RDIBits(10 downto 0);
RDIBits(0) <= InUartToUart;
end if;
end process;
I added some more things, like the entity, the IOs and a counter for the output register.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY my_uart IS
PORT(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- reset high active
---------------------------------------------
InUartToUart : IN std_logic;
DataOut : OUT std_logic_vector(11 downto 0)
);
END ENTITY;
ARCHITECTURE struct OF my_uart IS
signal RDIBits : std_logic_vector(11 downto 0);
signal counter : integer range 0 to 12;
begin
calc_proc: process(clk, rst)
begin
if (rst = '1') then
RDIBits <= (others => '0');
counter <= 0;
elsif ( rising_edge(clk) ) then
if (counter < 12) then
RDIBits <= RDIBits(10 downto 0) & InUartToUart;
counter <= counter + 1;
elsif (counter = 12) then
DataOut <= RDIBits;
counter <= 0;
end if;
end if;
end process;
END STRUCT;
This is a typical shift register application. For example:
signal RDIBits : std_logic_vector(11 downto 0);
...
process(clk)
begin
if ( rising_edge(clk) ) then
RDIBits <= RDIBits(10 downto 0) & InUartToUart;
end if;
end process;
I'm trying to make a 8-bit Sequential Multiplier on Quartus II. I did all the simulations of all blocks, but one is showing error on the VWF simulation. The sum_reg block it's doing a infinite shift in a very small time interval.
In the "dark blue" part of waveform simulation, on o_DOUT, it's when the shift gones infinite until the MSB goes to the LSB. The image below shows what happens in the dark blue part of the simulation:
Someone know what's happen?
Below the code:
Sum register(where the simulation goes wrong):
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sum_register is
port (
i_DIN : in UNSIGNED(8 DOWNTO 0);
i_LOAD : in STD_LOGIC;
i_CLEAR : in STD_LOGIC;
i_SHIFT : in STD_LOGIC;
o_DOUT : buffer UNSIGNED(15 downto 0)
);
end sum_register;
architecture arch_1 of sum_register is
begin
process(i_CLEAR,i_LOAD,i_SHIFT, i_DIN)
begin
IF (i_CLEAR = '1') THEN
o_DOUT <= "0000000000000000";
ELSIF (i_LOAD = '1') THEN
o_DOUT(15 downto 7) <= i_DIN;
ELSIF (i_SHIFT = '1') THEN
o_DOUT <= o_DOUT SRL 1;
END IF;
end process;
end arch_1;
You need to use a clock signal in the circuit to make this synchronous, you will need an input in your entity like this:
i_CLOCK : in STD_ULOGIC;
After this you will need to make your process sensitivy to the clock:
process(i_CLOCK)
And your architecture will change to this:
architecture arch_1 of sum_register is
SIGNAL r_DOUT : unsigned(15 downto 0);
begin
process(i_CLOCK)
begin
IF rising_edge(i_CLOCK) THEN
IF (i_CLEAR = '1') THEN
r_DOUT <= "0000000000000000";
ELSIF (i_LOAD = '1') THEN
r_DOUT(15 downto 8) <= i_DIN;
ELSIF (i_SHIFT = '1') THEN
r_DOUT <= r_DOUT SRL 1;
END IF;
END IF;
end process;
o_DOUT <= r_DOUT;
end arch_1;
With this architecture you will need a unsigned signal to make atribution for your output o_DOUT, with this you can change your o_DOUT output to output type again (not buffer).
NOTE: The clock signal needs to be the same for all blocks!
I'm looking for the correct syntax to build a generic line delay package using generics and for loops in a process. I understand that for loops when used with generate are for concurrent statements, but surely there must be a way to build it.
For example:
entity Delay_Line is
Generic (
CLK_DELAYS : integer := 10);
Port (
CLK : in STD_LOGIC;
i_Din : in STD_LOGIC;
o_Q : out STD_LOGIC;
o_Qnot : out STD_LOGIC);
end Delay_Line;
architecture Delay_Line_arch of Delay_Line is
signal din_dly : std_logic_vector(CLK_DELAYS-1 downto 0);
begin
din_dly(0) <= i_Din;
process(CLK)
begin
if rising_edge(CLK) then
for index in 0 to CLK_DELAYS-1 generate
begin
din_dly(index+1) <= din_dly(index);
end;
end if;
end process;
o_Q <= din_dly(CLK_DELAYS);
o_Qnot <= NOT (din_dly(CLK_DELAYS));
end Delay_Line_arch;
Typically I would just add a bunch of:
din_delay(9) <= din_delay(8);
din_delay(8) <= din_delay(7);
...
in the code, but honestly I'd like something a little more reusable as a package.
It isn't really necessary to use such elaborate methods to implement shift registers. You can implement them directly in one line using array concatenation and slicing.
constant DELAY_STAGES : positive := 10; -- Or use a generic parameter
signal delay_line : std_logic_vector(1 to DELAY_STAGES);
...
process(clk) is
begin
if rising_edge(clk) then
delay_line <= i_Din & delay_line(1 to DELAY_STAGES-1); -- Shift right
end if;
end process;
-- Retrieve the end of the delay without a hard-coded index
o_Q <= delay_line(delay_line'high);
The brevity of this approach pretty much eliminates any convenience of having a component that you need to instantiate with port and generic maps. Plus you have the flexibility of being able to tap off whatever intermediate signals you may need.
Well I don’t have 50 rep yet but to get Pablo R’s method to work with large busses and delays bus_size := 16 and delay := 256. I had to change:
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);
to
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (bus_size);
A bit late, but this is my generic_delay component:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY generic_delay is
generic (
bus_size : natural;
delay : natural
);
port (
i_Clock : IN STD_LOGIC;
i_reset : IN STD_LOGIC;
i_bus1 : in std_logic_vector(bus_size - 1 downto 0);
i_bus2 : in std_logic_vector(bus_size - 1 downto 0);
o_bus1 : out std_logic_vector(bus_size - 1 downto 0);
o_bus2 : out std_logic_vector(bus_size - 1 downto 0)
);
end generic_delay;
architecture a of generic_delay is
----------------------------
-- SIGNALS DECLARATION
----------------------------
signal temp_bus1 : std_logic_vector(delay*bus_size - 1 downto 0);
signal temp_bus2 : std_logic_vector(delay*bus_size - 1 downto 0);
BEGIN
-----------------------------------------
-- SYNCHRONOUS PROCESS
-----------------------------------------
process(i_Clock, i_reset)
begin
if i_reset = '1' then
temp_bus1 <= (others => '0');
temp_bus2 <= (others => '0');
elsif falling_edge(i_Clock) then
if delay > 1 then
temp_bus1 <= i_bus1 & temp_bus1(delay*bus_size - 1 downto (delay-1)*bus_size);
temp_bus2 <= i_bus2 & temp_bus2(delay*bus_size - 1 downto (delay-1)*bus_size);
else
temp_bus1 <= i_bus1;
temp_bus2 <= i_bus2;
end if;
elsif (RISING_EDGE(i_Clock)) then
o_bus1 <= temp_bus1(bus_size - 1 downto 0);
o_bus2 <= temp_bus2(bus_size - 1 downto 0);
end if; -- reset + rising_edge(clk)
end process logic;
-------------------------------------------------------
end a;
I have written the following VHDL code which is the component of a Fast Adder. The fast adder consists of an 8by8 register hooked up to adder whose code is below. How can i eliminate the use of inout Read_Adress. I want Read_Adress to be out std_logic_vector not inout?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
Entity Adder is
port(
Clock_50_MHZ :in std_logic;
En :in std_logic;
Data_Registerfile : in std_logic_vector(7 downto 0);
Read_Address: inout std_logic_vector(2 downto 0) := "000";
Output : out std_logic_vector(11 downto 0)
);
end Adder;
Architecture arch of Adder is
Signal result : unsigned (11 downto 0):="000000000000";
Signal regData: std_logic_vector(7 downto 0);
Begin
regData <= Data_Registerfile;
Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ) then
if (En = '1') then
if(Read_Address = "000") then
result <= "000000000000" + unsigned(regData);
Read_Address <= Read_Address + 1;
elsif(Read_Address = "111") then
Output <= std_logic_vector( result + unsigned(regData) );
Read_Address <= "000";
else
result <= result + unsigned(regData);
Read_Address <= Read_Address + 1;
end if;
end if;
end if;
End Process;
end arch;
This is a classic inconvenience in VHDL: you can't use your out ports as
signals (if you are used to Verilog, you often find yourself wanting to do
that).
The best way that I know of is to create an extra dummy signal:
signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";
do the computation with that:
Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ) then
if (En = '1') then
if(Read_Address_tmp = "000") then
result <= "000000000000" + unsigned(regData);
Read_Address_tmp <= Read_Address_tmp + 1;
elsif(Read_Address_tmp = "111") then
Output <= std_logic_vector( result + unsigned(regData) );
Read_Address_tmp <= "000";
else
result <= result + unsigned(regData);
Read_Address_tmp <= Read_Address_tmp + 1;
end if;
end if;
end if;
End Process;
and then link it to your output:
Read_Address <= Read_Address_tmp;
Owen's answer is the usual way, historically.
The "new" VHDL 2008 allows reading of out-mode ports now. If your tools don't support it, log a bug with the vendor. See the bottom of this page from "VHDL 2008 - just the new stuff"
http://books.google.co.uk/books?id=ETxLguPMEY0C&pg=PA163&lpg=PA163#v=onepage&q&f=false
This code should be (and is) very simple, and I don't know what I am doing wrong.
Here is description of what it should do:
It should display a number on one 7-segment display. That number should be increased by one every time someone presses the push button. There is also reset button which sets the number to 0. That's it. Here is VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Entity djelitelj (the counter used to divide 50MHz clock):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Debouncing entity:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= NOT PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '1';
ELSE
PB_DEBOUNCED <= '0';
End if;
end process;
end a;
And here is BCD to 7-segment decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder7seg is
port (
bcd: in std_logic_vector (3 downto 0);
segm: out std_logic_vector (6 downto 0));
end decoder7seg;
architecture Behavioral of decoder7seg is
begin
with bcd select
segm<= "0000001" when "0000", -- 0
"1001111" when "0001", -- 1
"0010010" when "0010", -- 2
"0000110" when "0011", -- 3
"1001100" when "0100", -- 4
"0100100" when "0101", -- 5
"0100000" when "0110", -- 6
"0001111" when "0111", -- 7
"0000000" when "1000", -- 8
"0000100" when "1001", -- 9
"1111110" when others; -- just - character
end Behavioral;
Does anyone see where I made my mistake(s) ?
I've tried that design on Spartan-3 Started board and it isn't working ... Every time I press the push button, I get crazy (random) values. The reset button is working properly.
Thanks !!!!
I guess the problem is here:
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
When rst='1' you will reset CurrentPWMState. But when inco='1' the you endlessly add 1 to CurrentPWMState. That's something like an asynchronous feedback loop through a latch. You should do something edge sensitive here. Probably you should capture inco using your clock signal, detect a 0->1 change and then add 1.
Agree with the previous answer.
A code like this should do the trick:
process (inco, ps, rst)
begin
if rst='1' then
CurrentPWMState <= '0';
prev_inco <= inco; -- This signal captures the previous value of inco
elsif ps'event and ps='1' then
if inco='1' and prev_inco='0' then -- Capture the flank rising.
CurrentPWMState <= CurrentPWMState + 1;
end if;
prev_inco <= inco;
end if;
end process;
I recognize I haven't tried the code (just coded in here) but I think it's ok.