Last day, last 3 hours before we give the project and we just realized we have this error!
I am not very good in vhdl so I can't understand what the problem is!
Error (10588): VHDL Generic Map Aspect error at addsub16.vhd(31): too many actuals for block "fulladder16" with only 0 formals
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY addsub16 IS
PORT(X, Y :IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Add_Sub :IN STD_LOGIC;
Result :OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
Cout :OUT STD_LOGIC;
Overflow :OUT STD_LOGIC);
END addsub16;
ARCHITECTURE Structure OF addsub16 IS
COMPONENT fulladder16
PORT(Cin :IN STD_LOGIC;
X, Y :IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Sum :OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
Cout :OUT STD_LOGIC;
Overflow :OUT STD_LOGIC);
END COMPONENT;
SIGNAL y_mod :STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
gen_XOR:
FOR i IN 0 TO 15 GENERATE
y_mod(i) <= Y(i) XOR Add_Sub;
END GENERATE;
adder:fulladder16 GENERIC MAP(16)
PORT MAP(Add_Sub, X, y_mod, Result, Cout, Overflow);
END Structure;
The problem is the line:
adder:fulladder16 GENERIC MAP(16)
The "formal" is a port, generic, etc. declared in the prototype for a component (or whatever). The "actual" is what's mapped to it.
You are mapping 1 actual value to a component (fulladder16) whose declaration (just above that in your code) shows 0 formal generics.
Related
I am making a 32 bit register with port and generic mapping. For some reason it says that the target signal Qt has 31 bits, while the input has 32 bits. Makes no sense right now. I looked through everything, and could not find how the Qt could be anything else than 32 bits since I declared the signal as signal Qt: std_logic_vector(31 downto 0);Any help is appreciated thanks.
I isolated the error line Qt <= D; and it still threw an exception. Down below is my minimally reproducible example.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
Did not realize that I had N: INTEGER:= 31 in the top file. When I changed the definition to N: INTEGER:= 32 the error disappeared. Sloppy coding on my part. I don't know why the tcl referenced this in the register file and not the top(lapfn) file. Is this because VHDL is written top down after port mapping, and it assumed the component from the top was the true bit-size?
entity LAPfn is
Port (resetn, clock, sclr, lap_db: in std_logic;
lap_select: in std_logic_vector (2 downto 0);
Data_in: in std_logic_vector (31 downto 0);
Lap_bits: out std_logic_vector (31 downto 0);
zlap: out std_logic;
cout: out std_logic_vector(2 downto 0));
end LAPfn;
architecture Behavioral of LAPfn is
component my_rege
generic (N: INTEGER:= 31);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
I am trying to run post synthesis functional simulation. When i run the code for behavioral simulation, i get the output and everything runs fine. Bu when i run the post synthesis i get the following error:
ERROR: [VRFC 10-3146] binding entity 'rippleadder_nbit' does not have generic 'n' [C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]
Can someone explain me what i need to do please. I am a novice in Vivado and very confused on how to use this
My Rippleadder Code is:
entity rippleadder_nbit is
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end rippleadder_nbit;
architecture Behavioral of rippleadder_nbit is
component fulladder port(
x_fa : in STD_LOGIC;
y_fa : in STD_LOGIC;
z_fa : in STD_LOGIC;
s_fa : out STD_LOGIC;
c_fa : out STD_LOGIC);
end component;
signal r: std_logic_vector(n downto 0);
begin
r(0) <= cin_ra;
cout_ra <= r(n);
FA: for i in 0 to n-1 generate
FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
end generate;
end Behavioral;
my testbench is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ripplenbit is
-- Port ( s: std_logic_vector(2 downto 0);
-- cout: std_logic);
end tb_ripplenbit;
architecture Behavioral of tb_ripplenbit is
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;
begin
a <= "0000", "0001" after 50 ns, "0101" after 100ns;
b <= "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;
UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);
end Behavioral;
In post-synthesis/post-implementation, the generics(constant) are deleted and usage of those generics are replaced with the constant value
In test bench, you had instance w.r.t to behavioural model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation
Source: Xilinx Forums
I'm writing something in VHDL about an essay and I'm facing a strange situation. I've written some components, simulated and tested them, and everything seems to works fine. However, when simulating the top entity, I'm getting zeros as a result! Please take a look at the following listings:
Top Entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity foobar is
port ( data_i : in std_logic_vector(39 downto 0);
sum_12bit_o : out std_logic_vector(11 downto 0)
);
end foobar;
architecture Behavioral of foobar is
--Declare components
component four_10bit_word_adder is
port( --Input signals
a_byte_in: in std_logic_vector(9 downto 0);
b_byte_in: in std_logic_vector(9 downto 0);
c_byte_in: in std_logic_vector(9 downto 0);
d_byte_in: in std_logic_vector(9 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(11 downto 0)
);
end component;
-- Signal declaration
signal int: std_logic_vector(11 downto 0);
signal intdata: std_logic_vector(39 downto 0);
begin
intdata <= data_i; --DEBUG
U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),
intdata(19 downto 10), intdata(9 downto 0),
'0', int);
end Behavioral;
four_10bit_word_adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_10bit_word_adder is
generic (
bits: integer := 10
);
port( --Input signals
a_byte_in: in std_logic_vector(bits-1 downto 0);
b_byte_in: in std_logic_vector(bits-1 downto 0);
c_byte_in: in std_logic_vector(bits-1 downto 0);
d_byte_in: in std_logic_vector(bits-1 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(bits+1 downto 0)
);
end four_10bit_word_adder;
architecture Behavioral of four_10bit_word_adder is
-- Component Declaration
component compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end component;
--------------------------------------------------------+
component generic_11bit_adder
port (
A: in std_logic_vector(10 downto 0); --Input A
B: in std_logic_vector(10 downto 0); --Input B
CI: in std_logic; --Carry in
O: out std_logic_vector(10 downto 0); --Sum
CO: out std_logic --Carry Out
);
end component;
--------------------------------------------------------+
-- Declare internal signals
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal
signal byte_out: std_logic_vector(bits-1 downto 0);
signal carry: std_logic_vector(bits-1 downto 0);
signal int11bit: std_logic_vector(bits downto 0);
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder.
-- See the paper for more info.
signal Concat_A: std_logic_vector(bits downto 0);
signal Concat_B: std_logic_vector(bits downto 0);
signal co : std_logic;
begin
A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),
c_byte_in(0), d_byte_in(0),
'0', int(0), byte_out(0), carry(0));
instances: for i in 1 to bits-1 generate
A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),
c_byte_in(i), d_byte_in(i), int(i-1),
int(i), byte_out(i), carry(i));
end generate;
R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co);
Concat_A <= int(8) & byte_out;
Concat_B <= carry & '0';
process (co)
begin
if (co = '1') then
val12bit_out <= '1' & int11bit;
else
val12bit_out <= '0' & int11bit;
end if;
end process;
end Behavioral;
4:2 Compressor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end compressor_4_2;
architecture Behavioral of compressor_4_2 is
-- Internal Signal Definitions
signal stage_1: std_logic;
begin
stage_1 <= d XOR (b XOR c);
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d));
sum <= (a XOR cin) XOR stage_1;
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1));
end Behavioral;
Generic 11-bit Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic_11bit_adder is
generic (
bits: integer := 11
);
port (
A: in std_logic_vector(bits-1 downto 0);
B: in std_logic_vector(bits-1 downto 0);
CI: in std_logic;
O: out std_logic_vector(bits-1 downto 0);
CO: out std_logic
);
end entity generic_11bit_adder;
architecture Behavioral of generic_11bit_adder is
begin
process(A,B,CI)
variable sum: integer;
-- Note: we have one bit more to store carry out value.
variable sum_vector: std_logic_vector(bits downto 0);
begin
-- Compute our integral sum, by converting all operands into integers.
sum := conv_integer(A) + conv_integer(B) + conv_integer(CI);
-- Now, convert back the integral sum into a std_logic_vector, of size bits+1
sum_vector := conv_std_logic_vector(sum, bits+1);
-- Assign outputs
O <= sum_vector(bits-1 downto 0);
CO <= sum_vector(bits); -- Carry is the most significant bit
end process;
end Behavioral;
I've tried a ton of things, but without any success. Do you have any idea what am I doing wrong? Sorry for the long question and thank you for your time.
Take a look at your process to generate val12bit_out in your four_10bit_word_adder entity. It's missing an input.
Also, there are several other issues. Fixing this one issue will not fix everything. But once you fix it, I think things will be a lot more clear.
I have an adder block and I need to feed the output (std_logic_vector) back to one of the adder's input ports to be added with another number (This is to be done in another entity where the adder is used.). I tried to do that thru a process with sensitivity list but it did not work. Is there a way to do so?
Note: no clocks are used.
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
entity example is
port (
X: IN std_logic_vector(15 downto 0);
Y: IN std_logic_vector(15 downto 0);
Z: OUT std_logic_vector(15 downto 0)
);
end example;
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s, ain, bin: std_logic_vector(15 downto 0);
signal cin, overflow, useless: std_logic;
begin
process(x, y) is
begin
ain <= x;
bin <= y;
cin <= '0';
end process;
process(s, overflow) is
begin
ain <= s;
bin <= "1111111110000001";
cin <= overflow;
end process;
U1: adder port map (ain, bin, cin, s, overflow);
z <= s;
end arch_example;
In your code, you have multiple drivers for the signals ain, bin, and cin because two processes are driving these signals at the same time. You can think of it as two gates driving the same wire.
To add another number to an intermediate result in a fully combinational design, you will need a second adder. The first adder cannot be re-used because you cannot easily tell, when to switch to the new inputs with multiplexers for example. (It will be possible with the concepts of asynchronous logic, but that is much more complex.)
A simple solution is to instantiate your adder component twice:
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (x, y, '0', s, overflow);
U2: adder port map (s, "1111111110000001", overflow, z, open);
end arch_example;
The code snippet above uses positional assignment of component ports. This should be avoided because one can easily mixup the order of the ports. I recommend to use named assignments instead. Here one can explictly see which port (on the left of =>) is assigned to which signal (on the right):
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (
a => x,
b => y,
cin => '0',
s => s,
overflow => overflow);
U2: adder port map (
a => s,
b => "1111111110000001",
cin => overflow,
s => z,
overflow => open);
end arch_example;
i am new to vhdl. i have a code with me as follows (the sub prog compiles very fine). i can't fix the following error
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(110): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(115): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(120): Illegal sequential statement.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): Illegal sequential statement.
** Warning: [14] C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(128): (vcom-1272) Length of formal "Remainder" is 4; length of actual is 8.
** Error: C:/Users/acer/Desktop/alu new/ALU_VHDL.vhd(138): VHDL Compiler exiting
the line nos are bold ones in the code here.they are the portmap ones
Can anyone please help me out with this. it would be very kind of you.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_VHDL is
port
(
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation: in std_logic_vector(2 downto 0);
Startt : in std_logic;
Ready : out std_logic;
Result_High : out std_logic_vector(3 downto 0);
Result_Low : out std_logic_vector(7 downto 0);
Errorsig : out std_logic;
Reset_n : in std_logic;
Clkk : in std_logic);
end entity ALU_VHDL;
architecture Behavioral of ALU_VHDL is
-- And gate
component AND_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- OR Gate
component OR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- XOR gate
component XOR_gate
port(
x,y : IN std_logic_vector(3 downto 0);
z : OUT std_logic_vector(3 downto 0));
end component;
-- Adder
COMPONENT adder4
PORT
(
C : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
C_out : OUT std_logic);
END COMPONENT;
-- Subtractor
COMPONENT Substractor4
PORT
(
br_in : IN std_logic;
x,y : IN std_logic_vector(3 DOWNTO 0);
R : OUT std_logic_vector(3 DOWNTO 0);
E : out std_logic);
END COMPONENT;
-- Multiplier
COMPONENT mult4by4
port(operA, operB: in std_logic_vector(3 downto 0);
sumOut: out std_logic_vector(7 downto 0));
END COMPONENT;
-- Division
COMPONENT Division
Port ( Dividend : in std_logic_vector(3 downto 0);
Divisor : in std_logic_vector(3 downto 0);
Start : in std_logic;
Clk : in std_logic;
Quotient : out std_logic_vector(3 downto 0);
Remainder : out std_logic_vector(3 downto 0);
Finish : out std_logic);
END COMPONENT;
begin
process(OperandA, OperandB, Startt, Operation) is
begin
case Operation is
when "000" =>
Result_High <= "XXXX";
when "001" =>
Result_High <= OperandA and OperandB;
when "010" =>
Result_High <= OperandA or OperandB;
when "011" =>
Result_High <= OperandA xor OperandB;
when "100" =>
-- Adder
**U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);**
when "101" =>
-- Substractor & Error signal
**U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);**
when "110" =>
-- multiplication
**U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);**
when "111" =>
-- Division
if (OperandB ="0000") then
Errorsig <= '1';
else
**U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);**
end if;
when others =>
Errorsig <= '1';
end case;
end process;
end architecture Behavioral;
You cannot instantiate entities within a process.
Move all entity instantiations out of the process (into the architecture body) and work from there.
If you want to in instantiate component depending on the value of 'Operation', like the zennehoy wrote, you should instantiate components out of the process and in this case statement only use signal connected to this components in instantiations and link it to port you want.
For the length issue change the "Remainder : out std_logic_vector(3 downto 0);"
to "Remainder : out std_logic_vector(7 downto 0);"