vhdl feedback the output of a block to its input - vhdl

Question

I have an adder block and I need to feed the output (std_logic_vector) back to one of the adder's input ports to be added with another number (This is to be done in another entity where the adder is used.). I tried to do that thru a process with sensitivity list but it did not work. Is there a way to do so?
Note: no clocks are used.
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
entity example is
port (
X: IN std_logic_vector(15 downto 0);
Y: IN std_logic_vector(15 downto 0);
Z: OUT std_logic_vector(15 downto 0)
);
end example;
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s, ain, bin: std_logic_vector(15 downto 0);
signal cin, overflow, useless: std_logic;
begin
process(x, y) is
begin
ain <= x;
bin <= y;
cin <= '0';
end process;
process(s, overflow) is
begin
ain <= s;
bin <= "1111111110000001";
cin <= overflow;
end process;
U1: adder port map (ain, bin, cin, s, overflow);
z <= s;
end arch_example;

Answer 1

In your code, you have multiple drivers for the signals ain, bin, and cin because two processes are driving these signals at the same time. You can think of it as two gates driving the same wire.
To add another number to an intermediate result in a fully combinational design, you will need a second adder. The first adder cannot be re-used because you cannot easily tell, when to switch to the new inputs with multiplexers for example. (It will be possible with the concepts of asynchronous logic, but that is much more complex.)
A simple solution is to instantiate your adder component twice:
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (x, y, '0', s, overflow);
U2: adder port map (s, "1111111110000001", overflow, z, open);
end arch_example;
The code snippet above uses positional assignment of component ports. This should be avoided because one can easily mixup the order of the ports. I recommend to use named assignments instead. Here one can explictly see which port (on the left of =>) is assigned to which signal (on the right):
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (
a => x,
b => y,
cin => '0',
s => s,
overflow => overflow);
U2: adder port map (
a => s,
b => "1111111110000001",
cin => overflow,
s => z,
overflow => open);
end arch_example;