Unable to run post synthesis vivado - vhdl

Question

I am trying to run post synthesis functional simulation. When i run the code for behavioral simulation, i get the output and everything runs fine. Bu when i run the post synthesis i get the following error:
ERROR: [VRFC 10-3146] binding entity 'rippleadder_nbit' does not have generic 'n' [C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]
Can someone explain me what i need to do please. I am a novice in Vivado and very confused on how to use this
My Rippleadder Code is:
entity rippleadder_nbit is
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end rippleadder_nbit;
architecture Behavioral of rippleadder_nbit is
component fulladder port(
x_fa : in STD_LOGIC;
y_fa : in STD_LOGIC;
z_fa : in STD_LOGIC;
s_fa : out STD_LOGIC;
c_fa : out STD_LOGIC);
end component;
signal r: std_logic_vector(n downto 0);
begin
r(0) <= cin_ra;
cout_ra <= r(n);
FA: for i in 0 to n-1 generate
FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
end generate;
end Behavioral;
my testbench is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ripplenbit is
-- Port ( s: std_logic_vector(2 downto 0);
-- cout: std_logic);
end tb_ripplenbit;
architecture Behavioral of tb_ripplenbit is
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;
begin
a <= "0000", "0001" after 50 ns, "0101" after 100ns;
b <= "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;
UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);
end Behavioral;

Answer 1

In post-synthesis/post-implementation, the generics(constant) are deleted and usage of those generics are replaced with the constant value
In test bench, you had instance w.r.t to behavioural model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation
Source: Xilinx Forums