I Write and decelerate this code in Modelsim but in my component i will get error "Can't resolve indexed name type std_ulogic as type std_logic_vector". how to fix it?
library IEEE;
use ieee.std_logic_1164.all,ieee.numeric_std.all,Work.all;
entity NbitCarrySkipAdder is
generic (n: integer :=8);
Port(A, B: in std_logic_vector (n-1 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector (n-1 downto 0);
Cout: out std_logic);
end NbitCarrySkipAdder;
architecture behavioral of NbitCarrySkipAdder is
component NBitBlockWithSkipAdder is
generic(n:integer:=4);
port( a, b : in std_logic_vector( n-1 downto 0);
Cin_Block : in std_logic;
S : out std_logic_vector( n-1 downto 0);
Cout_Block : out std_logic);
end component NBitBlockWithSkipAdder;
signal Carry: std_logic_vector(0 to n);
begin
g1: for i in 0 to n-1 generate
lt: if i = 0 generate
f0: NBitBlockWithSkipAdder port map (A(i),B(i),Cin,Sum(i),Carry(i+1));
end generate lt;
rt: if i = n-1 generate
fn: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Cout);
end generate rt;
md: if i > 0 and i < n-1 generate
fm: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Carry(i+1));
end generate md;
end generate g1;
end architecture behavioral;
deceleration of my component is same as deceleration in the above code.
thx
Problem is that A(i) is a std_logic in port map for NBitBlockWithSkipAdder, but a port is declared as std_logic_vector.
Either change the port type in NBitBlockWithSkipAdder to std_logic, or use a range of one element in A in order to get a std_logic_vector with a single bit, like A(i downto i), thus making instantiations like:
f0 : NBitBlockWithSkipAdder port map (A(i downto i), B(i downto i), Cin, Sum(i downto i), Carry(i+1));
Related
I am trying to create N-bits adder/subtractor using a ripple of full adders.
The input is N-bits A, N-bits B, and the result should be at length of 2N (it outputs ALU with 2 buses High and low of N-bits each, so I am trying to extend the signed bit).
The problem arises with carryout in subtraction. For example, when doing 3-2 (assume N=3 so that it's 011-010 and with two's compliment it's 011+110) I get 001 with carry 1. The problem is that this carry is garbage and can't be extended, but in other case it's necessary. For example, when trying do (-3)+(-3) (101+101, again N=3), then I get 010 with carry of 1. This time the carry really indicate the sign, so I would like to extend it.
Here is my code:
entity FullAdder is
Port (
A : in std_logic;
B : in std_logic;
Cin : in std_logic;
sum : out std_logic;
Cout : out std_logic
);
end FullAdder;
architecture gate of FullAdder is
begin
sum <= A xor B xor Cin ;
Cout <= (A and B) OR (Cin and A) OR (Cin and B) ;
end gate;
here is the N-bit Adder
entity NbitsAdder is
generic(N: integer := 8);
Port(
A : in std_logic_vector((N-1) downto 0);
B : in std_logic_vector((N-1) downto 0);
Cin: in std_logic;
SUM : out std_logic_vector((N-1) downto 0);
Cout : out std_logic
);
end NbitsAdder;
architecture NbitsAdderGate of NbitsAdder is
...
signal temp : std_logic_vector (N downto 0);
begin
temp (0) <= Cin;
arrrayOfFullAdders : for i in 0 to N-1 generate
adder_i: FullAdder port map ( A(i), B(i), temp(i), SUM(i), temp (i+1) );
end generate;
Cout <= temp(N); --which will be extend
end NbitsAdderGate;
And this is the ADDER or SUBTRACTOR
entity NbitsAddOrSub is
generic(N: integer := 8);
port(
A : in std_logic_vector ((N-1) downto 0);
B : in std_logic_vector ((N-1) downto 0);
addOrSub : in std_logic;
sumLo : out std_logic_vector ((N-1) downto 0);
sumHi : out std_logic_vector ((N-1) downto 0)
);
end NbitsAddOrSub;
architecture NbitsAddOrSubGate of NbitsAddOrSub is
signal tempB: std_logic_vector ( (N-1) downto 0);
signal CoutTemp: std_logic;
begin
loop1 : for i in 0 to N-1 generate
xor_i: xorGate port map ( B(i), addOrSub, tempB(i));
end generate;
theOperation : NbitsAdder generic map (N)
port map ( A => A, B => tempB, Cin => addOrSub, sum => sumLo, Cout => CoutTemp);
sumHi <= (N-1 downto 0 => CoutTemp); -- tring to extend the sign bit
end NbitsAddOrSubGate;
In signed addition the carry has no meaning. You get the sign bit from the MSB of the sum and not from the carry. In your second example there is an underflow because -3+-3 is smaller than 2^((N=3)-1), thus the result is incorrect.
To sign-extend the result you should first check the overflow/underflow conditions for signed addition. If no overflow/underflow has occured, you look at the MSB of the sum and extend that bit
When I try to simulate a program using the generate statement calling a component it gives an error saying to check previous errors. this is when I use the "gen: for i in 0 to n-1 generate". but when I change it to "gen: for i in n-1 to 0 generate" it will let me simulate it but when I try to use the component, a 'Full_adder', the output does not output the answer, it just stays 'UUUU'. Any ideas? Code is below.
entity comtest is
generic (n : positive := 16);
Port (
abus, bbus: in std_logic_vector(n-1 downto 0);
sbus: out std_logic_vector(n-1 downto 0);
cai: in std_logic;
cao: out std_logic);
end comtest;
architecture Behavioral of comtest is
component Full_adder is
generic(tpd: delay_length := 10ns);
port (a, b, ci: in std_logic;
s, co: out std_logic);
end component;
signal c: std_logic_vector(n-1 downto 0);
begin
gen: for i in 0 to n-1 generate
-- gen: for i in n-1 to 0 generate
fa: Full_adder port map (a => abus(i), b => bbus(i),ci => c(i-1), s => sbus(i), co => c(i));
end generate;
c(0) <= cai;
cao <= c(n-1);
end Behavioral;
Its probably something stupid but can get it to work. The full adder that I wrote works and the ports for it are declared correctly.
I'm writing something in VHDL about an essay and I'm facing a strange situation. I've written some components, simulated and tested them, and everything seems to works fine. However, when simulating the top entity, I'm getting zeros as a result! Please take a look at the following listings:
Top Entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity foobar is
port ( data_i : in std_logic_vector(39 downto 0);
sum_12bit_o : out std_logic_vector(11 downto 0)
);
end foobar;
architecture Behavioral of foobar is
--Declare components
component four_10bit_word_adder is
port( --Input signals
a_byte_in: in std_logic_vector(9 downto 0);
b_byte_in: in std_logic_vector(9 downto 0);
c_byte_in: in std_logic_vector(9 downto 0);
d_byte_in: in std_logic_vector(9 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(11 downto 0)
);
end component;
-- Signal declaration
signal int: std_logic_vector(11 downto 0);
signal intdata: std_logic_vector(39 downto 0);
begin
intdata <= data_i; --DEBUG
U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),
intdata(19 downto 10), intdata(9 downto 0),
'0', int);
end Behavioral;
four_10bit_word_adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_10bit_word_adder is
generic (
bits: integer := 10
);
port( --Input signals
a_byte_in: in std_logic_vector(bits-1 downto 0);
b_byte_in: in std_logic_vector(bits-1 downto 0);
c_byte_in: in std_logic_vector(bits-1 downto 0);
d_byte_in: in std_logic_vector(bits-1 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(bits+1 downto 0)
);
end four_10bit_word_adder;
architecture Behavioral of four_10bit_word_adder is
-- Component Declaration
component compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end component;
--------------------------------------------------------+
component generic_11bit_adder
port (
A: in std_logic_vector(10 downto 0); --Input A
B: in std_logic_vector(10 downto 0); --Input B
CI: in std_logic; --Carry in
O: out std_logic_vector(10 downto 0); --Sum
CO: out std_logic --Carry Out
);
end component;
--------------------------------------------------------+
-- Declare internal signals
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal
signal byte_out: std_logic_vector(bits-1 downto 0);
signal carry: std_logic_vector(bits-1 downto 0);
signal int11bit: std_logic_vector(bits downto 0);
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder.
-- See the paper for more info.
signal Concat_A: std_logic_vector(bits downto 0);
signal Concat_B: std_logic_vector(bits downto 0);
signal co : std_logic;
begin
A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),
c_byte_in(0), d_byte_in(0),
'0', int(0), byte_out(0), carry(0));
instances: for i in 1 to bits-1 generate
A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),
c_byte_in(i), d_byte_in(i), int(i-1),
int(i), byte_out(i), carry(i));
end generate;
R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co);
Concat_A <= int(8) & byte_out;
Concat_B <= carry & '0';
process (co)
begin
if (co = '1') then
val12bit_out <= '1' & int11bit;
else
val12bit_out <= '0' & int11bit;
end if;
end process;
end Behavioral;
4:2 Compressor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end compressor_4_2;
architecture Behavioral of compressor_4_2 is
-- Internal Signal Definitions
signal stage_1: std_logic;
begin
stage_1 <= d XOR (b XOR c);
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d));
sum <= (a XOR cin) XOR stage_1;
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1));
end Behavioral;
Generic 11-bit Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic_11bit_adder is
generic (
bits: integer := 11
);
port (
A: in std_logic_vector(bits-1 downto 0);
B: in std_logic_vector(bits-1 downto 0);
CI: in std_logic;
O: out std_logic_vector(bits-1 downto 0);
CO: out std_logic
);
end entity generic_11bit_adder;
architecture Behavioral of generic_11bit_adder is
begin
process(A,B,CI)
variable sum: integer;
-- Note: we have one bit more to store carry out value.
variable sum_vector: std_logic_vector(bits downto 0);
begin
-- Compute our integral sum, by converting all operands into integers.
sum := conv_integer(A) + conv_integer(B) + conv_integer(CI);
-- Now, convert back the integral sum into a std_logic_vector, of size bits+1
sum_vector := conv_std_logic_vector(sum, bits+1);
-- Assign outputs
O <= sum_vector(bits-1 downto 0);
CO <= sum_vector(bits); -- Carry is the most significant bit
end process;
end Behavioral;
I've tried a ton of things, but without any success. Do you have any idea what am I doing wrong? Sorry for the long question and thank you for your time.
Take a look at your process to generate val12bit_out in your four_10bit_word_adder entity. It's missing an input.
Also, there are several other issues. Fixing this one issue will not fix everything. But once you fix it, I think things will be a lot more clear.
I have an adder block and I need to feed the output (std_logic_vector) back to one of the adder's input ports to be added with another number (This is to be done in another entity where the adder is used.). I tried to do that thru a process with sensitivity list but it did not work. Is there a way to do so?
Note: no clocks are used.
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
entity example is
port (
X: IN std_logic_vector(15 downto 0);
Y: IN std_logic_vector(15 downto 0);
Z: OUT std_logic_vector(15 downto 0)
);
end example;
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s, ain, bin: std_logic_vector(15 downto 0);
signal cin, overflow, useless: std_logic;
begin
process(x, y) is
begin
ain <= x;
bin <= y;
cin <= '0';
end process;
process(s, overflow) is
begin
ain <= s;
bin <= "1111111110000001";
cin <= overflow;
end process;
U1: adder port map (ain, bin, cin, s, overflow);
z <= s;
end arch_example;
In your code, you have multiple drivers for the signals ain, bin, and cin because two processes are driving these signals at the same time. You can think of it as two gates driving the same wire.
To add another number to an intermediate result in a fully combinational design, you will need a second adder. The first adder cannot be re-used because you cannot easily tell, when to switch to the new inputs with multiplexers for example. (It will be possible with the concepts of asynchronous logic, but that is much more complex.)
A simple solution is to instantiate your adder component twice:
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (x, y, '0', s, overflow);
U2: adder port map (s, "1111111110000001", overflow, z, open);
end arch_example;
The code snippet above uses positional assignment of component ports. This should be avoided because one can easily mixup the order of the ports. I recommend to use named assignments instead. Here one can explictly see which port (on the left of =>) is assigned to which signal (on the right):
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (
a => x,
b => y,
cin => '0',
s => s,
overflow => overflow);
U2: adder port map (
a => s,
b => "1111111110000001",
cin => overflow,
s => z,
overflow => open);
end arch_example;
I'm trying to create an m bit adder by instantiating multiple copies of the n bit adder using for/generate loop. This is my code so far, it fails to simulate by giving the error:
"Line 44: Not all partial formals of a_n have actual". The n bit adder is declared as component, I have successfully tested it and it works.
Please help by offering any suggestions to solve this problem
entity m_bit_adder is
generic (m : integer := 16; n : integer := 4);
Port ( A_m : in STD_LOGIC_VECTOR (m-1 downto 0);
B_m : in STD_LOGIC_VECTOR (m-1 downto 0);
Cin_m : in STD_LOGIC;
Cout_m : out STD_LOGIC;
S_m : out STD_LOGIC_VECTOR (m-1 downto 0));
end m_bit_adder;
architecture Behavioral of m_bit_adder is
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end component;
signal sig_m : std_logic_vector (m downto 0);
begin
m_bit_adder : for j in 0 to m-1 generate
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
B_n(n-1)=> B_m(j),
S_n(n-1) => S_m(j),
Cin_n => sig_m(j),
Cout_n => sig_m(j+1)
);
end generate;
sig_m(0) <= Cin_m;
Cout_m <= sig_m(m);
end Behavioral;
This is my code for the n adder:
entity n_bit_adder is
generic (n : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end n_bit_adder;
architecture Behavioral of n_bit_adder is
component adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal sig_n : std_logic_vector (n downto 0);
begin
n_bit_adder : for i in 0 to n-1 generate
one_bit : adder
port map (
A => A_n(i),
B => B_n(i),
S => S_n(i),
Cin => sig_n(i),
Cout => sig_n(i+1)
);
end generate;
sig_n(0) <= Cin_n;
Cout_n <= sig_n(n);
end Behavioral;
The n_bit_adder is instantiated using only a single bit of the formal side with A_n(n-1) in:
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
....
But the component for n_bit_adder has as std_logic_vector for A_n with multiple bits in:
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
...
So for a std_logic_vector(3 downto 0) then A_n(2 downto 0) are not used on the formal side (left side) of the mapping, which is also what the error message says in "Not all partial formals of a_n have actual".
Note also, that it looks like different names n_number and n are used in component for generic and std_logic_vector length on ports.