When I try to simulate a program using the generate statement calling a component it gives an error saying to check previous errors. this is when I use the "gen: for i in 0 to n-1 generate". but when I change it to "gen: for i in n-1 to 0 generate" it will let me simulate it but when I try to use the component, a 'Full_adder', the output does not output the answer, it just stays 'UUUU'. Any ideas? Code is below.
entity comtest is
generic (n : positive := 16);
Port (
abus, bbus: in std_logic_vector(n-1 downto 0);
sbus: out std_logic_vector(n-1 downto 0);
cai: in std_logic;
cao: out std_logic);
end comtest;
architecture Behavioral of comtest is
component Full_adder is
generic(tpd: delay_length := 10ns);
port (a, b, ci: in std_logic;
s, co: out std_logic);
end component;
signal c: std_logic_vector(n-1 downto 0);
begin
gen: for i in 0 to n-1 generate
-- gen: for i in n-1 to 0 generate
fa: Full_adder port map (a => abus(i), b => bbus(i),ci => c(i-1), s => sbus(i), co => c(i));
end generate;
c(0) <= cai;
cao <= c(n-1);
end Behavioral;
Its probably something stupid but can get it to work. The full adder that I wrote works and the ports for it are declared correctly.
Related
I am doing my first project in VHDL, I try to implement 8-bit barrel shifter using mux.
This is code for one block (8 mux in chain):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;
-------------------------------------
ENTITY Shifter IS
GENERIC (n : INTEGER );
PORT ( x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
redB: IN Integer;
out_m: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Shifter;
--------------------------------------------------------------
ARCHITECTURE dfl OF Shifter IS
SIGNAL sm : STD_LOGIC;
SIGNAL what_b : STD_LOGIC;
BEGIN
--redB in the number of the red block in the diagram
--The first mux port map is the same for all three blocks
sm <= y(redB);
first : MUX port map(
a => x(0),
b => '0',
s0 => sm,
y => out_m(0)
);
b0: if redB=0 generate --First block - only the first mux has b=0
rest : for i in 1 to n-1 generate
chain : MUX port map(
a => x(i),
b => x(i-1),
s0 => sm,
y => out_m(i)
);
end generate;
end generate;
b1: if redB=1 generate
rest : for i in 1 to n-1 generate
what_b <= '0' when i=1 else --Second block - 2 first mux has b=0
x(i-2);
chain : MUX port map(
a => x(i),
b => what_b,
s0 => sm,
y => out_m(i)
);
end generate;
end generate;
b2: if redB=2 generate
rest : for i in 1 to n-1 generate
what_b <= '0' when i=1 or i=2 or i=3 else --Third block - 4 first mux has b=0
x(i-4);
chain : MUX port map(
a => x(i),
b => what_b,
s0 => sm,
y => out_m(i)
);
end generate;
end generate;
END dfl;
In this is the code for changing 3 shifters:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;
-------------------------------------
ENTITY Barrel IS
GENERIC (n : INTEGER);
PORT ( x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
out_shifter0,out_shifter1,out_shifter2: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Barrel;
--------------------------------------------------------------
ARCHITECTURE dfl OF Barrel IS
SIGNAL temp_out0 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out1 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out2 : std_logic_vector(n-1 DOWNTO 0);
BEGIN
y0: Shifter GENERIC MAP(n) port map (x=>x,y=>y,redB=>0,out_m=>temp_out0);
out_shifter0 <= temp_out0;
y1: Shifter GENERIC MAP(n) port map (x=>temp_out0,y=>y,redB=>1,out_m=>temp_out1);
out_shifter1 <= temp_out1;
y2: Shifter GENERIC MAP(n) port map (x=>temp_out1,y=>y,redB=>2,out_m=>temp_out2);
out_shifter2 <= temp_out2;
END dfl;
All the files are compiling, but when I try to run a simulation I get this warning:
# ** Warning: (vsim-8684) No drivers exist on out port /tb/L0/y1/out_m(7 downto 1), and its initial value is not used.
#
# Therefore, simulation behavior may occur that is not in compliance with
#
# the VHDL standard as the initial values come from the base signal /tb/L0/temp_out1(7 downto 1).
I am using ModelSim.
Anyone got any idea of what could be the problem?
Thanks!
You have done a generate with a signal, and compared its value to something. Integers initialise to -2^31, so none of the generate blocks exist because the values you have assigned externally do not get assigned until after the simulation is started, but the generates get created during elaboration (before the simulation starts) using the initial value of redB. Hence no drivers for out_m. Instead of using a signal in the generate condition, use generics instead, as their values are fixed and assigned during elaboration.
Can someone help me to create a TestBench Program for the below Program, please?
library ieee;
use ieee.std_logic_1164.all;
entity bitwise is
port( a,b : in std_logic_vector(4 downto 0);
result1, result2, result3, result4, result5, result6 : out std_logic_vector(4 downto 0));
end bitwise;
architecture arch of bitwise is
begin
result1 <= a and b;
result2 <= a or b;
result3 <= a xor b;
result4 <= not a;
result5 <= to_stdlogicvector(to_bitvector(a) sll 1);
result6 <= to_stdlogicvector(to_bitvector(a) srl 1);
end arch;
My Test Bench Program is below: I am stuck to in the Stimulus process where we have to test each and every possibility. It could be either a loop version or just testing possible numbers for each operator.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity test_bitwise is
end test_bitwise;
architecture behavior of test_bitwise is
component bitwise;
port( a,b : in std_logic_vector(4 downto 0);
result1, result2, result3, result4 : out std_logic_vector(4 downto 0));
end component;
--INPUTS
signal tb_a : std_logic_vector(4 downto 0) := (others => '0');
`signal tb_b : std_logic_vector(4 downto 0) := (others => '0');
--OUTPUTS
signal tb_result1 : std_logic_vector(7 downto 0);
signal tb_result2 : std_logic_vector(7 downto 0);
signal tb_result3 : std_logic_vector(7 downto 0);
signal tb_result4 : std_logic_vector(7 downto 0);
begin
-- INSTANTIATE THE UNIT UNDER TEST (UUT)
U1_Test : entity work.test_bitwise(behavioral)
port map (a => tb_a,
b => tb_b,
result1 <= tb_result1,
result2 <= tb_result2,
result3 <= tb_result3,
result4 <= tb_result4);
--STIMULUS PROCESS
stim_proc : process
begin
-- CODE HERE
end process;
end behavior;
As others have stated in the comments, you should provide some input yourself. What have you tried and why didn't it succeed? If you have hard time to find out what to try and how to start, you could begin by doing the following. And if you don't succeed, you can then edit your question or post a new one so the other members can help you.
Use a for loop to iterate over each and every possibility. Writing all the possible values to test by hand would be exhausting.
Because you have two inputs, use two nested for loops inside your process. One iterates the values for input a and the other one for b. Check here how a for loop is written.
Inside the loops, assign values to your signals tb_a and tb_b. The loop indices are integers, so you have to convert them to std_logic_vector type before assigning. Check here for a short tutorial about VHDL conversions.
Add some delay after each iteration with wait.
Print the output values for example to simulator console with report, or you can even use assert statement.
I have this very simple 16-bit and gate written in structural form in VHDL:
The files are uploaded here.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_16bit is
Port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
Clk : in STD_LOGIC;
--Rst : in STD_LOGIC;
C : out std_logic_vector(15 downto 0) );
end and_16bit;
architecture Behavioral of and_16bit is
component and_1bit is
Port (
A : in std_logic;
B : in std_logic;
C : out std_logic );
end component;
signal s : std_logic_vector(15 downto 0);
begin
ands: for i in 15 downto 0 generate
and_1bit_x: and_1bit port map (A => A(i), B => B(i), C => s(i));
end generate;
process(Clk)
begin
if rising_edge(Clk) then
C <= s;
end if;
end process;
end Behavioral;
In order to update the output in the rising edge of the clock, I have defined this "s" signal. I wonder if this is the correct way to update the output in structural VHDL codes? what should I do to scape the unknown output for the first output?
Any comments will be a great help.
It's better to put the sequential process into a submodule and instantiate it in the top-level (and_16bit). Then your top-level will be more structural.
You can have one instance for each bit as you did for and_1bit.
For example, this module is a 1-bit register.
entity dff_1bit is
Port (
D : in std_logic;
Clk : in std_logic;
Q : out std_logic );
end dff_1bit;
architecture Behavioral of dff_1bit is
begin
process(Clk)
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;
end Behavioral;
Then you can instantiate it in and_16bit, inside the same generate block.
dff_1bit_x: dff_1bit port map (D => s(i), Clk => Clk, Q => C(i));
I have an adder block and I need to feed the output (std_logic_vector) back to one of the adder's input ports to be added with another number (This is to be done in another entity where the adder is used.). I tried to do that thru a process with sensitivity list but it did not work. Is there a way to do so?
Note: no clocks are used.
Here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
entity example is
port (
X: IN std_logic_vector(15 downto 0);
Y: IN std_logic_vector(15 downto 0);
Z: OUT std_logic_vector(15 downto 0)
);
end example;
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s, ain, bin: std_logic_vector(15 downto 0);
signal cin, overflow, useless: std_logic;
begin
process(x, y) is
begin
ain <= x;
bin <= y;
cin <= '0';
end process;
process(s, overflow) is
begin
ain <= s;
bin <= "1111111110000001";
cin <= overflow;
end process;
U1: adder port map (ain, bin, cin, s, overflow);
z <= s;
end arch_example;
In your code, you have multiple drivers for the signals ain, bin, and cin because two processes are driving these signals at the same time. You can think of it as two gates driving the same wire.
To add another number to an intermediate result in a fully combinational design, you will need a second adder. The first adder cannot be re-used because you cannot easily tell, when to switch to the new inputs with multiplexers for example. (It will be possible with the concepts of asynchronous logic, but that is much more complex.)
A simple solution is to instantiate your adder component twice:
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (x, y, '0', s, overflow);
U2: adder port map (s, "1111111110000001", overflow, z, open);
end arch_example;
The code snippet above uses positional assignment of component ports. This should be avoided because one can easily mixup the order of the ports. I recommend to use named assignments instead. Here one can explictly see which port (on the left of =>) is assigned to which signal (on the right):
architecture arch_example of example is
component adder is
port(a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
cin: in std_logic;
s: out std_logic_vector(15 downto 0);
overflow: out std_logic);
end component;
signal s : std_logic_vector(15 downto 0);
signal overflow : std_logic;
begin
U1: adder port map (
a => x,
b => y,
cin => '0',
s => s,
overflow => overflow);
U2: adder port map (
a => s,
b => "1111111110000001",
cin => overflow,
s => z,
overflow => open);
end arch_example;
I Write and decelerate this code in Modelsim but in my component i will get error "Can't resolve indexed name type std_ulogic as type std_logic_vector". how to fix it?
library IEEE;
use ieee.std_logic_1164.all,ieee.numeric_std.all,Work.all;
entity NbitCarrySkipAdder is
generic (n: integer :=8);
Port(A, B: in std_logic_vector (n-1 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector (n-1 downto 0);
Cout: out std_logic);
end NbitCarrySkipAdder;
architecture behavioral of NbitCarrySkipAdder is
component NBitBlockWithSkipAdder is
generic(n:integer:=4);
port( a, b : in std_logic_vector( n-1 downto 0);
Cin_Block : in std_logic;
S : out std_logic_vector( n-1 downto 0);
Cout_Block : out std_logic);
end component NBitBlockWithSkipAdder;
signal Carry: std_logic_vector(0 to n);
begin
g1: for i in 0 to n-1 generate
lt: if i = 0 generate
f0: NBitBlockWithSkipAdder port map (A(i),B(i),Cin,Sum(i),Carry(i+1));
end generate lt;
rt: if i = n-1 generate
fn: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Cout);
end generate rt;
md: if i > 0 and i < n-1 generate
fm: NBitBlockWithSkipAdder port map (A(i),B(i),Carry(i),Sum(i),Carry(i+1));
end generate md;
end generate g1;
end architecture behavioral;
deceleration of my component is same as deceleration in the above code.
thx
Problem is that A(i) is a std_logic in port map for NBitBlockWithSkipAdder, but a port is declared as std_logic_vector.
Either change the port type in NBitBlockWithSkipAdder to std_logic, or use a range of one element in A in order to get a std_logic_vector with a single bit, like A(i downto i), thus making instantiations like:
f0 : NBitBlockWithSkipAdder port map (A(i downto i), B(i downto i), Cin, Sum(i downto i), Carry(i+1));