Using for loop to design adder in vhdl - for-loop

Question

I'm trying to create an m bit adder by instantiating multiple copies of the n bit adder using for/generate loop. This is my code so far, it fails to simulate by giving the error:
"Line 44: Not all partial formals of a_n have actual". The n bit adder is declared as component, I have successfully tested it and it works.
Please help by offering any suggestions to solve this problem
entity m_bit_adder is
generic (m : integer := 16; n : integer := 4);
Port ( A_m : in STD_LOGIC_VECTOR (m-1 downto 0);
B_m : in STD_LOGIC_VECTOR (m-1 downto 0);
Cin_m : in STD_LOGIC;
Cout_m : out STD_LOGIC;
S_m : out STD_LOGIC_VECTOR (m-1 downto 0));
end m_bit_adder;
architecture Behavioral of m_bit_adder is
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end component;
signal sig_m : std_logic_vector (m downto 0);
begin
m_bit_adder : for j in 0 to m-1 generate
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
B_n(n-1)=> B_m(j),
S_n(n-1) => S_m(j),
Cin_n => sig_m(j),
Cout_n => sig_m(j+1)
);
end generate;
sig_m(0) <= Cin_m;
Cout_m <= sig_m(m);
end Behavioral;
This is my code for the n adder:
entity n_bit_adder is
generic (n : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
B_n : in STD_LOGIC_vector(n-1 downto 0);
Cin_n : in STD_LOGIC;
S_n : out STD_LOGIC_vector(n-1 downto 0);
Cout_n : out STD_LOGIC);
end n_bit_adder;
architecture Behavioral of n_bit_adder is
component adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal sig_n : std_logic_vector (n downto 0);
begin
n_bit_adder : for i in 0 to n-1 generate
one_bit : adder
port map (
A => A_n(i),
B => B_n(i),
S => S_n(i),
Cin => sig_n(i),
Cout => sig_n(i+1)
);
end generate;
sig_n(0) <= Cin_n;
Cout_n <= sig_n(n);
end Behavioral;

Answer 1

The n_bit_adder is instantiated using only a single bit of the formal side with A_n(n-1) in:
n_bit : n_bit_adder generic map (n_number => n)
port map (
A_n(n-1) => A_m(j),
....
But the component for n_bit_adder has as std_logic_vector for A_n with multiple bits in:
component n_bit_adder is
generic (n_number : integer := 4);
Port ( A_n : in STD_LOGIC_vector(n-1 downto 0);
...
So for a std_logic_vector(3 downto 0) then A_n(2 downto 0) are not used on the formal side (left side) of the mapping, which is also what the error message says in "Not all partial formals of a_n have actual".
Note also, that it looks like different names n_number and n are used in component for generic and std_logic_vector length on ports.