Illegal Sequential Statement Error on ModelSim - vhdl

Question

I'm trying to implement a testbench on Quartus II for a Discrete-Time FIR Filter. The testbench will read the input code from a .txt file and write the output onto another .txt file.
When I click on the RTL simulation button, the following errors appear on ModelSim:
Error: filter2/simulation/modelsim/filter.vht(83): Illegal sequential statement.
Error: filter2/simulation/modelsim/filter.vht(111): No feasible entries for subprogram "read".
Error: filter2/simulation/modelsim/filter.vht(147): VHDL Compiler exiting
How solve these errors? The code I've written is:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_textio.all;
USE STD.TEXTIO.ALL;
USE ieee.std_logic_arith.all;
ENTITY filter_vhd_tst IS
END filter_vhd_tst;
ARCHITECTURE filter_arch OF filter_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL clk_enable : STD_LOGIC;
SIGNAL filter_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL filter_out : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
signal flag : std_LOGIC := '0';
COMPONENT filter
PORT (
clk : IN STD_LOGIC;
clk_enable : IN STD_LOGIC;
filter_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
filter_out : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
reset : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : filter
PORT MAP (
-- list connections between master ports and signals
clk => clk,
clk_enable => clk_enable,
filter_in => filter_in,
filter_out => filter_out,
reset => reset
);
init : PROCESS
-- variable declarations
--constant clk_period : time := 20ns;
BEGIN
-- code that executes only once
clk_enable <= '1';
reset <= '0';
clk <= '0';
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
clk_process:PROCESS
BEGIN
clk <= '0';
wait for 10 ns; --clk_period/2;
clk <= '1';
wait for 10 ns; --clk_period/2;
end process;
--Stimulus
stim:process
begin
wait for 100 ns;
wait for 2000 ns;--clk_period*100;
wait for 50 us;
--inserting stimulus
wait;
end process;
process(clk)
file in_file : text open READ_MODE is "wave.txt";
variable in_line : LINE;
variable filed : integer range 0 to 65535;
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '1')then
if(divider = 0)then
if NOT ENDFILE(in_file)then
READLINE(in_file, in_line);
READ(in_file, filed);
filter_in <= conv_std_logic_vector(filed,16);
else
flag <= '1';
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
process(clk)
file RESULT_FILE: text open WRITE_MODE is "out.txt";
variable outline : LINE;
variable temp : std_LOGIC_VECTOR(32 downto 0);
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '0')then
if(divider = 0)then
if(flag = '0')then
temp := filter_out;
write(outline, temp);
writeLine(RESULT_FILE, outline);
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
--WAIT;
END PROCESS always;
END filter_arch;

Answer 1

The first error, line 83, is because of a process in a process:
always : PROCESS
BEGIN
clk_process : PROCESS
and since a process declaration is not a sequential statement, you get the error message:
Error: filter2/simulation/modelsim/filter.vht(83): Illegal sequential statement.
Second error is because read takes line as first argument, but is given file:
READ(in_file, filed);
so change to:
READ(in_line, filed);