I am working on frequency divider with an option to select out frequency, and I can't get this working. Syntax check passes every time, but when I start simulation I get this error: "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.20 - Internal Compiler Error in file ../src/VhdlTreeTransform.cpp at line 296 For technical support on this issue, please visit http://www.xilinx.com/support."
I already search for this problem and can't find any solution. I'm new in this and it's probably some banal problem, and I would be happy if You can help me with this.
The main code is here:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Freq4Sel is
Port ( cp : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0);
outcp : buffer STD_LOGIC:= '0');
end Freq4Sel;
architecture Behavioral of Freq4Sel is
begin
process(cp)
variable selects : integer range 0 to 50000000;
variable temp: integer range 0 to 50000000 := 0;
begin
with sel select
selects := 50000000 when "11",
5000000 when "10",
2000000 when "01",
1000000 when others;
if (cp'event and cp = '1') then
temp := temp+1;
if(temp>=selects) then
outcp <= not outcp;
end if;
end if;
end process;
end Behavioral;
And file for simulation test is here:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Freq4Sel_w IS
END Freq4Sel_w;
ARCHITECTURE behavior OF Freq4Sel_w IS
COMPONENT Freq4Sel
PORT(
cp : IN std_logic;
sel : IN std_logic_vector(1 downto 0);
outcp : BUFFER std_logic
);
END COMPONENT;
signal cp : std_logic := '0';
signal sel : std_logic_vector(1 downto 0) := "00";
signal outcp : std_logic;
constant cp_period : time := 10 ns;
BEGIN
uut: Freq4Sel PORT MAP (
cp => cp,
sel => sel,
outcp => outcp
);
cp_process :process
begin
cp <= '0';
wait for cp_period/2;
cp <= '1';
wait for cp_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
sel <= "10";
wait for cp_period*10;
wait;
end process;
END;
Related
I have an array of arrays defined as the input to my entity. I used a package to define the array of arrays. In the test bench, I included that package and declared the component in the architecture but there is an error saying "formal port x does not exist in entity average. Please compare the definition of block average to its component declaration and its instantion to detect the mismatch."
Attaching the declarations below. Please help.
-- the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package vpkg is
type m_array is array(1 downto 0, 1 downto 0) of std_logic_vector(7 downto 0);
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity average is
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end average;
architecture avg_arch of average is
signal sum : std_logic_vector(8 downto 0) := (others => '0');
begin
process(x):
for I in 0 to 1 loop
for J in 0 to 1 loop
sum <= sum + ('0' + x(I,J));
end loop;
end loop;
end process;
y <= std_logic_vector(to_signed(to_integer(signed(sum) / 4),8));
end avg_arch;
--the test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity tb_average is
-- Port ( );
end tb_average;
architecture tb_average_arch of tb_average is
component average
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end component;
signal x : m_array;
signal clk : std_logic := '0';
signal y : std_logic_vector(7 downto 0);
begin
average_1 : average Port Map (x => x,clk => clk,y=>y);
input_proc : process
begin
wait for 100ns;
x(0,0) <= "00001001";
x(0,1) <= "00000110";
x(1,0) <= "00000011";
x(1,1) <= "00000001";
wait;
end process;
clk_proc : process
begin
wait for 100ns;
loop
clk <= '1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end loop;
end process;
end tb_average_arch;
Please take a look at the following code, specifically the 3 commented lines at the end. I simulated this with Questasim 10.6c:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk : in std_logic
);
end alias_extname_driving_signal;
architecture primary of alias_extname_driving_signal is
signal buried_control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
begin
buried_control_vector16 <= std_logic_vector(unsigned(buried_control_vector16) + 1) when rising_edge(clk);
end architecture primary;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal_tb is
end alias_extname_driving_signal_tb;
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
-- vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
-- vector16 <= control_vector16_alias; -- this statement works
-- vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end architecture primary;
As you can see, I'm able to drive a signal with an external name, an alias of a local signal, but not an alias of an external name. Is there any way I can use an alias of an external name to drive a signal in vhdl-2008?
Thanks in advance for your help.
External names can only be declared AFTER the object being referenced is elaborated.
VHDL starts elaborating from the testbench. First it elaborates the declaration region. Then it elaborates the code region in order. If it finds a component, it elaborates it and any subcomponents. When it finishes elaborating the component (and any subcomponents) it picks up elaborating int the testbench where it left off.
Hence, you need to move your alias declaration to either a block statement or a process. The code for the block statement is as follows. Note the label with the block statement is required.
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
myblock : block
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
begin
vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
vector16 <= control_vector16_alias; -- this statement works
vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end block myblock ;
end architecture primary;
I'm a newbie in VHDL and hardware world.
I'm trying to make a Count&Compare example using Top Level Hierarchy and test it with testbench and see the results on ISIM.
Here is my block diagram sketch:
So I end up these 3 vhd source files:
Counter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Count_src is
Port ( CLK : in STD_LOGIC;
Reset : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0));
end Count_src;
architecture Behavioral of Count_src is
signal count : STD_LOGIC_VECTOR (3 downto 0);
begin
process (Reset, CLK)
begin
if Reset = '1' then -- Active high reset
count <= "0000"; -- Clear count to 0
elsif (rising_edge(CLK)) then -- Positive edge
count <= count + "0001"; -- increment count
end if;
end process;
S <= count; -- Export count
end Behavioral;
Compare
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Compare_src is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC);
end Compare_src;
architecture Behavioral of Compare_src is
begin
S <= '1' when (A = B) else -- Test if A and B are same
'0'; -- Set when S is different
end Behavioral;
CountCompare (Top Level)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CountCompare_src is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Value : in STD_LOGIC_VECTOR (3 downto 0);
Flag : out STD_LOGIC);
end CountCompare_src;
architecture Behavioral of CountCompare_src is
-- COMPONENT DECLERATIONS
component counter is
port ( CLK : in std_logic;
Reset : in std_logic;
S : out std_logic_vector(3 downto 0)
);
end component;
component compare is
port (A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : out std_logic
);
end component;
-- Component Spesification and Binding
for all : counter use entity work.Count_src(behavioral);
for all : compare use entity work.Compare_src(behavioral);
-- Internal Wires
signal count_out : std_logic_vector(3 downto 0);
begin
-- Component instantiation
C1: counter PORT MAP ( Reset => Reset,
CLK => Clock,
S => count_out
);
C2: compare PORT MAP ( A => count_out,
B => Value,
S => Flag
);
end Behavioral;
To test the design I wrote a testbench as follows:
TestBench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TopLevelTester_tb IS
END TopLevelTester_tb;
ARCHITECTURE behavior OF TopLevelTester_tb IS
--Input and Output definitions.
signal Clock : std_logic := '0';
signal Reset : std_logic := '0';
signal Value : std_logic_vector(3 downto 0) := "1000";
signal Flag : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.CountCompare_src PORT MAP
(
Clock => Clock,
Reset => Reset,
Value => Value
);
proc: process
begin
Clock <= '0';
wait for clk_period/2;
Clock <= '1';
wait for clk_period/2;
end process;
END;
When I simulate behavioral model, the ISIM pops up, but I see no changes on the Compare Flag. Here is the ss of the ISIM:
What am I missing here? Why does'nt the Flag change?
My best regards.
You have two problems, both in your testbench.
The first is that you never reset count in the counter, it will always be 'U's or 'X's (after you increment it).
The second is that the directly entity instantiation in the testbench is missing an association for the formal flag output to the actual flag signal:
begin
uut:
entity work.countcompare_src
port map (
clock => clock,
reset => reset,
value => value,
flag => flag
);
proc:
process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
if now > 20 ns then
wait;
end if;
end process;
stimulus:
process
begin
wait for 1 ns;
reset <= '1';
wait for 1 ns;
reset <= '0';
wait;
end process;
Fix those two things and you get:
I am trying to run a code that I have picked up online, but it somehow the testbench is failing to run the expected output on GHDL.
Architecture Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk200Hz is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clk200Hz;
architecture Behavioral of clk200Hz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 124999 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 124999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
clk_in : IN std_logic;
reset : IN std_logic;
clk_out: OUT std_logic
);
END COMPONENT;
-- Inputs
signal clk_in : std_logic := '0';
signal reset : std_logic := '0';
-- Outputs
signal clk_out : std_logic;
constant clk_in_t : time := 20 ns;
BEGIN
-- Instance of unit under test.
uut: clk200Hz PORT MAP (
clk_in => clk_in,
reset => reset,
clk_out => clk_out
);
-- Clock definition.
entrada_process :process
begin
clk_in <= '0';
wait for clk_in_t / 2;
clk_in <= '1';
wait for clk_in_t / 2;
end process;
-- Processing.
stimuli: process
begin
reset <= '1'; -- Initial conditions.
wait for 100 ns;
reset <= '0'; -- Down to work!
wait;
end process;
END;
I expect a wave that would form a clock pulsing up and down, however that does not seem to be the case. I wonder what is wrong with the design.
I ran the following commands:
ghdl -s *.vhd
ghdl -a *.vhd
ghdl -e clk200Hz_tb
ghdl -r clk200Hz_tb --vcd=led.vcd
gtkwave led.vcd
and this is my output
but for clock out, I expect a up and down signal, not a signal of 0.
Thanks
I have fixed the problem, in my running command, I simply added ghdl -r clk200Hz_tb --vcd=led.vcd --stop-time=100ns.
ghdl -a clk200Hz_tb.vhdl
ghdl -e clk200Hz_tb
ghdl -r clk200Hz_tb --wave=clk200hz_tb.ghw --stop-time=500ns
Gave:
(clickable)
The code is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clk_div is
Port (
clk_in : in STD_LOGIC;
clk_out_rx : out std_logic;
out_bit_parity : out std_logic
);
end clk_div;
architecture Behavioral of clk_div is
signal clk_slow_tx : std_logic := '0';
signal q : unsigned(9 downto 0) := (others => '0');
begin
process ( clk_in ) is
begin
if rising_edge(clk_in) then
q <= q + 1;
clk_slow_tx <= q(8); --- 58.gdfg/2^8 =~ 230Khz baud rate = 115200
clk_out_rx <= clk_slow_tx;
end if;
end process;
end Behavioral;
I am adding the testbench waveform of the above code:
If you need the testbench code I can write that also.
The output out_bit_parity is not assigned in the module, but the other output clk_out_rx toggles fine:
Test bench added below on request:
library ieee;
use ieee.std_logic_1164.all;
entity mdl_tb is
end entity;
library ieee;
use ieee.numeric_std.all;
architecture sim of mdl_tb is
constant CLK_FREQ : real := 100.0E6; -- Clock frequency in Hz
signal clk : std_logic;
signal dut_clk_out_rx : std_logic;
signal dut_out_bit_parity : std_logic;
begin
process is
begin
while TRUE loop
clk <= '1';
wait for 0.5 sec / CLK_FREQ;
clk <= '0';
wait for (1.0 sec / CLK_FREQ) - (0.5 sec / CLK_FREQ);
end loop;
end process;
mdl_e : entity work.clk_div
port map(
clk_in => clk,
clk_out_rx => dut_clk_out_rx,
out_bit_parity => dut_out_bit_parity);
end architecture;