I am facing a issue regarding Modelsim. I am not able to load my testbench in simulation. following is my testbench and code
Testbench
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
library work;
use work.pack1.all;
entity test_dg is
end entity;
architecture behavior of test_dg is
component digit_ext is
generic (
add_width : integer := 12; -- length of the adress of the node
depth : integer := 15);
port (
suc_add : in std_logic_vector(add_width-1 downto 0); -- source address
des_add : in std_logic_vector(add_width-1 downto 0); -- destination address
flg2 : out std_logic;
flg3 : out std_logic;
flg4 : out std_logic;
flg5 : out std_logic;
flg6 : out std_logic);
end component;
signal sucadd_t: std_logic_vector(11 downto 0) := "000000000000";
signal desadd_t: std_logic_vector(11 downto 0) := "000000000000";
begin
logic_instance: digit_ext port map (sucadd_t,desadd_t);
source_address: process
begin
sucadd_t <= "100000000000";
wait for 20 ns;
sucadd_t <= "000000000000";
wait for 20 ns;
end process;
destination_address: process
begin
desadd_t <= "010000000000";
wait for 23 ns;
desadd_t <= "001100000000";
wait for 44 ns;
desadd_t <= "001000000001";
wait for 65 ns;
desadd_t <= "000100100000";
wait for 86 ns;
end process;
endsumulation:process
begin
wait for 150 ns;
assert false report "end simulation" severity failure;
end process;
end behavior;
configuration CFG_LOG of test_dg is
for behavior
for logic_instance: digit_ext
end for;
end for;
end CFG_LOG;
Code:
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- =============================================================================
library work;
use work.pack1.all;
-- =============================================================================
entity digit_ext is
generic (
add_width : integer := 12; -- length of the adress of the node
depth : integer := 15);
port (
suc_add : in std_logic_vector(add_width-1 downto 0); -- source address
des_add : in std_logic_vector(add_width-1 downto 0); -- destination address
flg2 : out std_logic;
flg3 : out std_logic;
flg4 : out std_logic;
flg5 : out std_logic;
flg6 : out std_logic);
end digit_ext;
-- =============================================================================
architecture behavior of digit_ext is
type info is array (0 to depth) of integer;
signal self_info: info := (500,4,0,0,3,0,0,2,0,1,1,2,0);
signal equ_add : integer;
signal i1: integer;
signal i2: integer;
signal i3: integer;
signal flg1 : integer := 0;
signal v1 : integer;
signal v2 : std_logic := '0';
signal v3 : std_logic := '0';
signal v4 : std_logic := '0';
signal v5 : std_logic := '0';
signal v6 : std_logic := '0';
begin
-- =============================================================================
flg2 <= v2; -- assignment of signal to the output ports
flg3 <= v3;
flg4 <= v4;
flg5 <= v5;
flg6 <= v6;
-- =============================================================================
step1:process (des_add,equ_add,i1,i2,i3) -- to convert bcd address of destination to integer and to split the digits
begin
bcd_conv(des_add,equ_add,i1,i2,i3);
v1 <= (equ_add - self_info(1)); -- find distance between the current address and destination address
if (v1 < 0) then
flg1 <= 1;
elsif (v1 > 0 ) then
flg1 <= 2;
elsif (v1 = 0) then
flg1 <= 3;
end if;
end process;
-- =============================================================================
step2:process(flg1) -- process to find the up or down neighbour based on set value of flag
begin
if (flg1 = 1) then
v2 <= compare (i1,i2,i3,self_info(2),self_info(3),self_info(4));
v3 <= compare (i1,i2,i3,self_info(5),self_info(6),self_info(7));
elsif (flg1 = 2) then
v4 <= compare (i1,i2,i3,self_info(8),self_info(9),self_info(10));
v5 <= compare (i1,i2,i3,self_info(11),self_info(12),self_info(13));
elsif (flg1 = 3)then
v6 <= '1';
v2 <= '0';
v3 <= '0';
v4 <= '0';
v5 <= '0';
end if;
end process;
-- =============================================================================
end behavior;
-- =============================================================================
when I simulate the testbench , it say that no design loaded....
Thanks
Manasi.
Goto: http://www.synthworks.com/downloads/
Get the file: modelsim_tutorial.pdf and modelsim_quickref.pdf
Work through the tutorial. Compile the package (pack1). Then compile your design (digit_ext) and your testbench (test_dg). Note that you will not see the flags in the testbench unless you map them.
Related
I've been asked at the university to make a 4-bit bidirectional shift register. I did it first this way:
-- bidirektionale shift register mit data-load und serielle(R/L) output
library ieee;
use ieee.std_logic_1164.all;
entity bi_shift_reg is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Serial Shift-Right output
s_dout_L: out std_logic -- Serial Shift-Left output
);
end bi_shift_reg;
architecture arch of bi_shift_reg is
begin
process(clk,set,n_reset)
begin
-- reset (low aktiv)
if n_reset = '0' then dout <= "0000";
-- set
elsif set = '1' then dout <= "1111";
-- data-load
elsif(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
dout <= din;
-- shift right
elsif(rising_edge(clk) and sR = '1') then
s_dout_R <= din(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
s_dout_L <= din(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end process;
end arch;
but then I heard that I needed to use my previous coded D-Flipflop as a component for the shift register. So my question is: since I have new inputs (data_load,shift_left and shift_right) and outputs(Serial Shift-Right, Serial Shift-Left) how can I add them in my code along with the d-ff component? is it possible to use a component and process together ?
This is my d-ff code with asynchronous activ-low reset and asynchronous set:
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk,set,n_reset)
variable temp: std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
How can I use my flipflop to achieve the same result as the code for the shift-register ?
Thank you in advance for your answers :D
After several good questions in the comment track by the OP, it is reasonable to post some design that can serve as an example for a solution.
Please note, that there was not any precise specification of the intended operation, e.g. what is priority between different inputs, and how should timing be for outputs, so the code below is provided with the intention of showing some VHDL structures that may works as a template for further update by the OP.
--###############################################################################
-- d_flipflop
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
begin
process(clk, set, n_reset)
variable temp : std_logic; -- zwischenergebniss
begin
if n_reset = '0' then
temp := '0';
elsif set = '1' then
temp := '1';
elsif rising_edge(clk) then
temp := d;
end if;
q <= temp;
qn <= not temp;
end process;
end arch;
--###############################################################################
-- bi_shiftReg_ff
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port(din : in std_logic_vector(3 downto 0);
set, n_reset : in std_logic;
sR, sL : in std_logic; -- Shift-Right/Shift-Left
data_load : in std_logic;
clk : in std_logic;
dout : out std_logic_vector(3 downto 0);
s_dout_R : out std_logic; -- Shift-Right output
s_dout_L : out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
-- FF component
component d_flipflop is
port(d, clk, set, n_reset : in std_logic;
q, qn : out std_logic
);
end component;
-- FF data input
signal d : std_logic_vector(3 downto 0);
-- FF data output
signal q : std_logic_vector(3 downto 0);
signal qn : std_logic_vector(3 downto 0); -- Unused, but included for completness
begin
-- Combinatorial process, thus making gates only
process (all)
begin
-- data-load
if (data_load = '1') then
d <= din;
-- shift right; priority over shift left
elsif (sR = '1') then
d <= '0' & q(q'left downto 1); -- Discard right-most bit in the right shift
-- shift left
elsif (sL = '1') then
d <= q(q'left - 1 downto 0) & '0'; -- Discard left-most bit in the left shift
end if;
end process;
-- State held in FFs
GEN_REG : for i in 0 to 3 generate
REGX : d_flipflop port map
(d(i), clk, set, n_reset, q(i), qn(i));
end generate;
-- Outputs drive
dout <= q;
s_dout_R <= q(q'right); -- Bit 0, but shown with VHDL attributes
s_dout_L <= q(q'left); -- Bit 3, --||--
end arch;
--###############################################################################
-- EOF
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sqwaveGen is
port (
clk : in std_logic;
clk_out : out std_logic;
fall : in unsigned(7 downto 0);
reset : in std_logic;
rise : in unsigned(7 downto 0)
);
end entity;
architecture from_verilog of sqwaveGen is
signal count : unsigned(7 downto 0); -- Declared at design.sv:7
signal count_off : unsigned(7 downto 0); -- Declared at design.sv:7
signal count_on : unsigned(7 downto 0); -- Declared at design.sv:7
signal pos_or_neg : std_logic; -- Declared at design.sv:8
begin
clk_out <= pos_or_neg;
process (clk, reset) is
begin
if (not reset) = '1' then
count <= X"00";
count <= X"00";
pos_or_neg <= '1';
elsif rising_edge(clk) then
if (unsigned'("0000000000000000000000000000000") & pos_or_neg) = X"00000001" then
if Resize(count, 32) = (Resize(count_on, 32) - X"00000001") then
count <= X"00";
pos_or_neg <= '0';
else
count <= count + X"01";
end if;
else
if (unsigned'("0000000000000000000000000000000") & pos_or_neg) = X"00000000" then
if Resize(count, 32) = (Resize(count_off, 32) - X"00000001") then
count <= X"00";
pos_or_neg <= '1';
else
count <= count + X"01";
end if;
end if;
end if;
end if;
end process;
process (fall, rise) is
begin
count_on <= rise;
count_off <= fall;
end process;
end architecture;
You're trying to simulate a VHDL design with Icarus (iverilog) simulator, which is a Verilog simulator and does not support VHDL!
Use should use a simulator which supports VHDL, such as GHDL or Xilinx Vivado. Also save the file with ".vhd" or ".vhdl" extension.
I want to make 4kb byte addressable memory. sorry I'm new in VHDL
I wanted my code works first write 4byte number in adress 8 (rdwr=1, addr=1000, size=10(2^2byte), idata=10001100)
then wait 8 cycles to implement writing time(ivalid=0)
Second read 4byte number from adress 8(rdwr=0, addr=1000, size=10(2^2byte))
In my purpose, the "ready" signal should be '0' while waiting for writing time
but the signal is always 'U' in simulation. I tried to figure out what is the problem but i couldn't
Can anyone help me where did a make mistake?
Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Memory is
port (
clk: in std_logic;
ready: out std_logic; -- 0: busy, 1: ready
ivalid: in std_logic; -- 0: invalid, 1: valid
rdwr: in std_logic; -- 0: read, 1: write
addr: in unsigned(11 downto 0); -- byte address
size: in std_logic_vector(1 downto 0); -- 00/01/10/11: 1/2/4/8 bytes
idata: in std_logic_vector(63 downto 0);
ovalid: out std_logic; -- 0: invalid, 1: valid
odata: out std_logic_vector(63 downto 0)
);
end entity;
architecture Behavioral of Memory is
type ram_type is array (0 to (2**12)-1) of std_logic_vector(7 downto 0);
signal RAM : ram_type;
signal state : std_logic := '1'; --if ready '1'
signal queue : std_logic := '0'; --if something to do '1'
signal timer : integer := 0; --timer
signal curr_addr : unsigned(11 downto 0);
signal curr_size : std_logic_vector(1 downto 0);
signal curr_data : std_logic_vector(63 downto 0);
signal write : std_logic := '0';
signal read : std_logic := '0';
begin
process(clk)
variable vstate : std_logic := state;
variable vqueue : std_logic := queue; --if something to do '1'
variable vtimer : integer := timer; --timer
variable vcurr_addr : unsigned(11 downto 0) := curr_addr;
variable vcurr_size : std_logic_vector(1 downto 0) := curr_size;
variable vcurr_data : std_logic_vector(63 downto 0) := curr_data;
variable vwrite : std_logic := write;
variable vread : std_logic := read;
begin
--get input
if(rising_edge(clk)) then
ovalid <= '0';
if(vstate='1') then
if(ivalid='1') then
vcurr_addr := addr;
vcurr_size := size;
if(rdwr='0') then
--read
vread := '1';
else
vwrite := '1';
vcurr_data := idata;
end if;
vqueue := '1';
vtimer := 2**(to_integer(unsigned(vcurr_size)))-1;
end if;
end if;
--process
if(vqueue = '1') then
if(vtimer > 0) then
--wait for next cycle
ready <= '0';
vstate := '0';
vtimer := vtimer - 1;
else
--ok to go
if(vwrite = '1') then
--write
for x in 0 to 2**(to_integer(unsigned(vcurr_size)))-1 loop
for y in 0 to 7 loop
RAM(to_integer(vcurr_addr) + x)(y) <= vcurr_data(y + 8*x);
end loop;
end loop;
elsif(vread = '1') then
--read
for x in 0 to 7 loop
for y in 0 to 7 loop
if(x < 2**(to_integer(unsigned(vcurr_size)))) then
odata(y + 8*x) <= RAM(to_integer(vcurr_addr) + x)(y);
else
odata(y + 8*x) <= '0';
end if;
end loop;
end loop;
ovalid <= '1';
end if;
vqueue := '0';
vstate := '1';
ready <= '1';
end if;
end if;
--save variable to signals
state <= vstate;
queue <= vqueue;
timer <= vtimer;
curr_addr <=vcurr_addr;
curr_size <=vcurr_size;
curr_data<= vcurr_data;
write <= vwrite;
read <= vread;
end if;
end process;
end architecture;
I'm trying to implement a testbench on Quartus II for a Discrete-Time FIR Filter. The testbench will read the input code from a .txt file and write the output onto another .txt file.
When I click on the RTL simulation button, the following errors appear on ModelSim:
Error: filter2/simulation/modelsim/filter.vht(83): Illegal sequential statement.
Error: filter2/simulation/modelsim/filter.vht(111): No feasible entries for subprogram "read".
Error: filter2/simulation/modelsim/filter.vht(147): VHDL Compiler exiting
How solve these errors? The code I've written is:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_textio.all;
USE STD.TEXTIO.ALL;
USE ieee.std_logic_arith.all;
ENTITY filter_vhd_tst IS
END filter_vhd_tst;
ARCHITECTURE filter_arch OF filter_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL clk_enable : STD_LOGIC;
SIGNAL filter_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL filter_out : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
signal flag : std_LOGIC := '0';
COMPONENT filter
PORT (
clk : IN STD_LOGIC;
clk_enable : IN STD_LOGIC;
filter_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
filter_out : OUT STD_LOGIC_VECTOR(32 DOWNTO 0);
reset : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : filter
PORT MAP (
-- list connections between master ports and signals
clk => clk,
clk_enable => clk_enable,
filter_in => filter_in,
filter_out => filter_out,
reset => reset
);
init : PROCESS
-- variable declarations
--constant clk_period : time := 20ns;
BEGIN
-- code that executes only once
clk_enable <= '1';
reset <= '0';
clk <= '0';
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
clk_process:PROCESS
BEGIN
clk <= '0';
wait for 10 ns; --clk_period/2;
clk <= '1';
wait for 10 ns; --clk_period/2;
end process;
--Stimulus
stim:process
begin
wait for 100 ns;
wait for 2000 ns;--clk_period*100;
wait for 50 us;
--inserting stimulus
wait;
end process;
process(clk)
file in_file : text open READ_MODE is "wave.txt";
variable in_line : LINE;
variable filed : integer range 0 to 65535;
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '1')then
if(divider = 0)then
if NOT ENDFILE(in_file)then
READLINE(in_file, in_line);
READ(in_file, filed);
filter_in <= conv_std_logic_vector(filed,16);
else
flag <= '1';
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
process(clk)
file RESULT_FILE: text open WRITE_MODE is "out.txt";
variable outline : LINE;
variable temp : std_LOGIC_VECTOR(32 downto 0);
variable divider : integer range 0 to 499 := 499;
begin
if(clk'event and clk = '0')then
if(divider = 0)then
if(flag = '0')then
temp := filter_out;
write(outline, temp);
writeLine(RESULT_FILE, outline);
end if;
divider := 499;
else
divider := divider - 1;
end if;
end if;
end process;
--WAIT;
END PROCESS always;
END filter_arch;
The first error, line 83, is because of a process in a process:
always : PROCESS
BEGIN
clk_process : PROCESS
and since a process declaration is not a sequential statement, you get the error message:
Error: filter2/simulation/modelsim/filter.vht(83): Illegal sequential statement.
Second error is because read takes line as first argument, but is given file:
READ(in_file, filed);
so change to:
READ(in_line, filed);
I want to implement a random-number game on BASYS2. In this game there would be five LEDs chosen out of which one would turn on at random for a second or two (this time can be changed to increase or decrease the difficulty level of the game). Then the user is required to respond to this LED event by pressing the switch button behind it within the time that it is on. If he or she is able to do so successfully a point would be scored and it would be showed on the Seven Segment Display. If he or she fails no point would be scored. There would be 9 such events after which the game can be replayed.
Now following is my code (only for the random LED turning on). However, I am unable to fix it. Please somebody help. The FPGA I am using is BASYS2 SPARTAN 3E-100.
Thanks in advance to everyone.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity random_number is
generic ( width : integer := 4 );
port (
clk : in std_logic;
reset : in std_logic;
random_num : out std_logic_vector (width-1 downto 0) --output vector
);
end random_number;
architecture Behavioral of random_number is
signal q: std_logic_vector(23 downto 0);
signal divided_clock: std_logic;
begin
process(clk, reset)
begin
if (reset = '1')then
q <= X"000000";
elsif(rising_edge(clk)) then
q <= q + 1;
end if;
end process;
divided_clock <= q(22);
process (divided_clock)
variable rand_temp : std_logic_vector(width-1 downto 0):=("1000");
variable temp : std_logic := '0';
begin
if(rising_edge(divided_clock)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end Behavioral;
I think the second process should even run with the main clk and the devided clock should be an enable.
signal divided_enable: std_logic;
process(clk, reset)
begin
if (reset = '1')then
q <= X"000000";
elsif(rising_edge(clk)) then
q <= q + 1;
end if;
if (q(22) = '1') then
--short pulse wenn q bit 22 is high
divided_enable <= '1';
q <= (others => '0');
end if;
end process;
process (clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=("1000");
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
if(divided_enable = '1') then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
end if;
random_num <= rand_temp;
end process;
I don't know if this will fix all your problems. Please discribe compiler errors or errors in the behavior.