I am trying to make an ALU for floating point numbers.This is my code and whenever I try to run simulation of a testbench waveform simulator crashes stating this:
isim_beh.exe has stopped working
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fp is
port( in_one:in std_logic_vector(31 downto 0);
in_two:in std_logic_vector(31 downto 0);
select_line:in std_logic_vector(2 downto 0);
output:out std_logic_vector(31 downto 0));
end fp;
architecture Behavioral of fp is
signal bb:std_logic_vector(31 downto 0);
signal j,k,l:std_logic_vector(31 downto 0);
component floating
port (ina,inb:in std_logic_vector(31 downto 0);
sss:in std_logic_vector(2 downto 0);
outb:out std_logic_vector(31 downto 0));
end component;
component adder
port( a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
sss:in std_logic_vector(2 downto 0);
oo:out std_logic_vector(31 downto 0));
end component;
begin
u1:floating port map(in_one,in_two,select_line,j); --When ss=10 then multiply is chosen
u2:adder port map(in_one,in_two,select_line,k); --When ss=00 then addition is chosen and when ss=01 then subtraction is chosen
output<=(not in_one) when select_line="100" else
(in_one and in_two) when select_line="101" else
(in_one or in_two) when select_line="110" else
j+k;
end Behavioral;
PS Floating is the component for multiplication. Adder is the component for addition and subtraction.
Related
I am making a 32 bit register with port and generic mapping. For some reason it says that the target signal Qt has 31 bits, while the input has 32 bits. Makes no sense right now. I looked through everything, and could not find how the Qt could be anything else than 32 bits since I declared the signal as signal Qt: std_logic_vector(31 downto 0);Any help is appreciated thanks.
I isolated the error line Qt <= D; and it still threw an exception. Down below is my minimally reproducible example.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
Did not realize that I had N: INTEGER:= 31 in the top file. When I changed the definition to N: INTEGER:= 32 the error disappeared. Sloppy coding on my part. I don't know why the tcl referenced this in the register file and not the top(lapfn) file. Is this because VHDL is written top down after port mapping, and it assumed the component from the top was the true bit-size?
entity LAPfn is
Port (resetn, clock, sclr, lap_db: in std_logic;
lap_select: in std_logic_vector (2 downto 0);
Data_in: in std_logic_vector (31 downto 0);
Lap_bits: out std_logic_vector (31 downto 0);
zlap: out std_logic;
cout: out std_logic_vector(2 downto 0));
end LAPfn;
architecture Behavioral of LAPfn is
component my_rege
generic (N: INTEGER:= 31);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity my_rege is
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E, sclr: in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end my_rege;
architecture Behavioral of my_rege is
signal Qt: std_logic_vector (31 downto 0);
begin
Qt <= D;
Q <= Qt;
end Behavioral;
Compiling a project in VHDL on Modelsim I encountered the following errors:** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(15): near "architecture": syntax error ** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(24): near "reg_process": (vcom-1576) expecting END.
This is my code:
enter code here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity asic is
port ( ck,reset:in std_logic;
req_in: in std_logic_vector(1 downto 0);
req_out: out std_logic_vector(1 downto 0);
req_in_word, response_in_data, nanoinstruction: in std_logic_vector(49 downto 0);
req_out_word, response_out_data: out std_logic_vector(49 downto 0);
response_in, response_out_ack, req_out_ack: in std_logic;
response_out, response_in_ack, req_in_ack: out std_logic);
end asic;
architecture asic_rtl of asic is
signal state,next_state: integer;
signal tmp_source1,tmp_source2 : std_logic_vector(15 downto 0);
signal value1, value2 : std_logic_vector(31 downto 0);
type regsarray IS array (0 to 2**12-1) OF std_logic_vector(49 downto 0);
signal reg_file : regsarray;
signal tmp_nanoinstruction: std_logic_vector(49 downto 0);
signal rw: std_logic;
begin
reg_process:process(ck,reset)
begin
if reset='1' then
state<=1;
elsif rising_edge(ck) then
state<= next_state;
end if;
end process reg_process;
emphasized text
I don't understand what I'm doing wrong.
Thank you in advance.
I agree with Matthew Taylor: the architecture needs to be closed.
Try to add the following to the end of your file:
end asic_rtl;
I am trying to run post synthesis functional simulation. When i run the code for behavioral simulation, i get the output and everything runs fine. Bu when i run the post synthesis i get the following error:
ERROR: [VRFC 10-3146] binding entity 'rippleadder_nbit' does not have generic 'n' [C:/Users/gauta/Assignment4/Assignment4.srcs/sim_1/new/tb_ripplenbit.vhd:41]
Can someone explain me what i need to do please. I am a novice in Vivado and very confused on how to use this
My Rippleadder Code is:
entity rippleadder_nbit is
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end rippleadder_nbit;
architecture Behavioral of rippleadder_nbit is
component fulladder port(
x_fa : in STD_LOGIC;
y_fa : in STD_LOGIC;
z_fa : in STD_LOGIC;
s_fa : out STD_LOGIC;
c_fa : out STD_LOGIC);
end component;
signal r: std_logic_vector(n downto 0);
begin
r(0) <= cin_ra;
cout_ra <= r(n);
FA: for i in 0 to n-1 generate
FA_i : fulladder port map(r(i),a(i),b(i),s_ra(i),r(i+1));
end generate;
end Behavioral;
my testbench is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ripplenbit is
-- Port ( s: std_logic_vector(2 downto 0);
-- cout: std_logic);
end tb_ripplenbit;
architecture Behavioral of tb_ripplenbit is
component rippleadder_nbit
generic(n: natural);
Port ( cin_ra : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
s_ra : out STD_LOGIC_VECTOR (n-1 downto 0);
cout_ra : out STD_LOGIC);
end component;
signal a,b,sin : STD_LOGIC_VECTOR (3 downto 0);
signal cin,carry_out : std_logic;
constant c : integer :=4;
begin
a <= "0000", "0001" after 50 ns, "0101" after 100ns;
b <= "0010", "0011" after 50 ns, "1010" after 100 ns;
cin <= '1', '0' after 50 ns;
UUT1 : rippleadder_nbit generic map(n => c) port map(cin_ra => cin,a=>a,b=>b,s_ra=>sin,cout_ra =>carry_out);
end Behavioral;
In post-synthesis/post-implementation, the generics(constant) are deleted and usage of those generics are replaced with the constant value
In test bench, you had instance w.r.t to behavioural model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation
Source: Xilinx Forums
I'm writing something in VHDL about an essay and I'm facing a strange situation. I've written some components, simulated and tested them, and everything seems to works fine. However, when simulating the top entity, I'm getting zeros as a result! Please take a look at the following listings:
Top Entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity foobar is
port ( data_i : in std_logic_vector(39 downto 0);
sum_12bit_o : out std_logic_vector(11 downto 0)
);
end foobar;
architecture Behavioral of foobar is
--Declare components
component four_10bit_word_adder is
port( --Input signals
a_byte_in: in std_logic_vector(9 downto 0);
b_byte_in: in std_logic_vector(9 downto 0);
c_byte_in: in std_logic_vector(9 downto 0);
d_byte_in: in std_logic_vector(9 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(11 downto 0)
);
end component;
-- Signal declaration
signal int: std_logic_vector(11 downto 0);
signal intdata: std_logic_vector(39 downto 0);
begin
intdata <= data_i; --DEBUG
U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),
intdata(19 downto 10), intdata(9 downto 0),
'0', int);
end Behavioral;
four_10bit_word_adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_10bit_word_adder is
generic (
bits: integer := 10
);
port( --Input signals
a_byte_in: in std_logic_vector(bits-1 downto 0);
b_byte_in: in std_logic_vector(bits-1 downto 0);
c_byte_in: in std_logic_vector(bits-1 downto 0);
d_byte_in: in std_logic_vector(bits-1 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(bits+1 downto 0)
);
end four_10bit_word_adder;
architecture Behavioral of four_10bit_word_adder is
-- Component Declaration
component compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end component;
--------------------------------------------------------+
component generic_11bit_adder
port (
A: in std_logic_vector(10 downto 0); --Input A
B: in std_logic_vector(10 downto 0); --Input B
CI: in std_logic; --Carry in
O: out std_logic_vector(10 downto 0); --Sum
CO: out std_logic --Carry Out
);
end component;
--------------------------------------------------------+
-- Declare internal signals
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal
signal byte_out: std_logic_vector(bits-1 downto 0);
signal carry: std_logic_vector(bits-1 downto 0);
signal int11bit: std_logic_vector(bits downto 0);
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder.
-- See the paper for more info.
signal Concat_A: std_logic_vector(bits downto 0);
signal Concat_B: std_logic_vector(bits downto 0);
signal co : std_logic;
begin
A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),
c_byte_in(0), d_byte_in(0),
'0', int(0), byte_out(0), carry(0));
instances: for i in 1 to bits-1 generate
A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),
c_byte_in(i), d_byte_in(i), int(i-1),
int(i), byte_out(i), carry(i));
end generate;
R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co);
Concat_A <= int(8) & byte_out;
Concat_B <= carry & '0';
process (co)
begin
if (co = '1') then
val12bit_out <= '1' & int11bit;
else
val12bit_out <= '0' & int11bit;
end if;
end process;
end Behavioral;
4:2 Compressor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end compressor_4_2;
architecture Behavioral of compressor_4_2 is
-- Internal Signal Definitions
signal stage_1: std_logic;
begin
stage_1 <= d XOR (b XOR c);
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d));
sum <= (a XOR cin) XOR stage_1;
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1));
end Behavioral;
Generic 11-bit Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic_11bit_adder is
generic (
bits: integer := 11
);
port (
A: in std_logic_vector(bits-1 downto 0);
B: in std_logic_vector(bits-1 downto 0);
CI: in std_logic;
O: out std_logic_vector(bits-1 downto 0);
CO: out std_logic
);
end entity generic_11bit_adder;
architecture Behavioral of generic_11bit_adder is
begin
process(A,B,CI)
variable sum: integer;
-- Note: we have one bit more to store carry out value.
variable sum_vector: std_logic_vector(bits downto 0);
begin
-- Compute our integral sum, by converting all operands into integers.
sum := conv_integer(A) + conv_integer(B) + conv_integer(CI);
-- Now, convert back the integral sum into a std_logic_vector, of size bits+1
sum_vector := conv_std_logic_vector(sum, bits+1);
-- Assign outputs
O <= sum_vector(bits-1 downto 0);
CO <= sum_vector(bits); -- Carry is the most significant bit
end process;
end Behavioral;
I've tried a ton of things, but without any success. Do you have any idea what am I doing wrong? Sorry for the long question and thank you for your time.
Take a look at your process to generate val12bit_out in your four_10bit_word_adder entity. It's missing an input.
Also, there are several other issues. Fixing this one issue will not fix everything. But once you fix it, I think things will be a lot more clear.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity buffer_d_e is
port(
clk:in std_logic;
clr:in std_logic;
in_RegDst:in std_logic;
out_RegDst:out std_logic;
in_MemRead:in std_logic;
out_MemRead:out std_logic;
in_MemtoReg:in std_logic;
out_MemtoReg:out std_logic;
in_MemWrite:in std_logic;
out_MemWrite:out std_logic;
in_ALUop:in std_logic_vector(1 downto 0);
out_ALUop:out std_logic_vector(1 downto 0);
in_ALUsrc:in std_logic;
out_ALUsrc:out std_logic;
in_RegWrite:in std_logic;
out_RegWrite:out std_logic;
in_read_data_1:in std_logic_vector(31 downto 0);
out_read_data_1:out std_logic_vector(31 downto 0);
in_read_data_2:in std_logic_vector(31 downto 0);
out_read_data_2:out std_logic_vector(31 downto 0);
in_sign_ext:in std_logic_vector(31 downto 0);
out_sign_ext:out std_logic_vector(31 downto 0);
in_func:in std_logic_vector(5 downto 0);
out_func:out std_logic_vector(5 downto 0);
in_instr_20_16:in std_logic_vector(4 downto 0);
out_instr_20_16:out std_logic_vector(4 downto 0);
in_instr_15_11:in std_logic_vector(4 downto 0);
out_instr_15_11:out std_logic_vector(4 downto 0);
in_instr_25_21:in std_logic_vector(4 downto 0);
out_instr_25_21:out std_logic_vector(4 downto 0)
);
end buffer_d_e;
architecture behavioral of buffer_d_e is
signal s_RegDst,s_MemRead,s_MemtoReg,s_MemWrite,s_ALUsrc,s_RegWrite:std_logic;
signal s_ALUop:std_logic_vector(1 downto 0);
signal s_instr_20_16,s_instr_15_11,s_instr_25_21:std_logic_vector(4 downto 0);
signal s_func:std_logic_vector(5 downto 0);
signal s_read_data_1,s_read_data_2,s_sign_ext:std_logic_vector(31 downto 0);
begin
process(clk,clr)
begin
if clr='1'
then
s_RegDst<='X';
s_MemRead<='X';
s_MemtoReg<='X';
s_MemWrite<='X';
s_ALUop<="XX";
s_ALUsrc<='X';
s_RegWrite<='X';
s_read_data_1<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_read_data_2<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_sign_ext<="XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
s_func<="XXXXXX";
s_instr_20_16<="XXXXX";
s_instr_15_11<="XXXXX";
s_instr_25_21<="XXXXX";
elsif clk'event AND clk='1'
THEN
s_RegDst<=in_RegDst;
s_MemRead<=in_MemRead;
s_MemtoReg<=in_MemtoReg;
s_MemWrite<=in_MemWrite;
s_ALUop<=in_ALUop;
s_ALUsrc<=in_ALUsrc;
s_RegWrite<=in_RegWrite;
s_read_data_1<=in_read_data_1;
s_read_data_2<=in_read_data_2;
s_sign_ext<=in_sign_ext;
s_func<=in_func;
s_instr_20_16<=in_instr_20_16;
s_instr_15_11<=in_instr_15_11;
s_instr_25_21<=in_instr_25_21;
end if;
out_RegDst<=s_RegDst;
out_MemRead<=s_MemRead;
out_MemtoReg<=s_MemtoReg;
out_MemWrite<=s_MemWrite;
out_ALUop<=s_ALUop;
out_ALUsrc<=s_ALUsrc;
out_RegWrite<=s_RegWrite;
out_read_data_1<=s_read_data_1;
out_read_data_2<=s_read_data_2;
out_sign_ext<=s_sign_ext;
out_func<=s_func;
out_instr_20_16<=s_instr_20_16;
out_instr_15_11<=s_instr_15_11;
out_instr_25_21<=s_instr_25_21;
end process;
end behavioral;
Code above is a simple code for buffer. 'clr' is a clear signal, 'clk'is a clock. My confusion is that the simulation result of this buffer shows the input and output time interval is 1.5 clock cycle rather than 1 clock cycle.(s_addr1_same and s_rse are input and output of buffer respectively) But why it happens and how to solve this? Thanks in advance.