Compile a project in VHDL on Modelsim - vhdl

Compiling a project in VHDL on Modelsim I encountered the following errors:** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(15): near "architecture": syntax error ** Error: C:/Users/User.User-PC/Desktop/progettoasi.vhd(24): near "reg_process": (vcom-1576) expecting END.
This is my code:
enter code here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity asic is
port ( ck,reset:in std_logic;
req_in: in std_logic_vector(1 downto 0);
req_out: out std_logic_vector(1 downto 0);
req_in_word, response_in_data, nanoinstruction: in std_logic_vector(49 downto 0);
req_out_word, response_out_data: out std_logic_vector(49 downto 0);
response_in, response_out_ack, req_out_ack: in std_logic;
response_out, response_in_ack, req_in_ack: out std_logic);
end asic;
architecture asic_rtl of asic is
signal state,next_state: integer;
signal tmp_source1,tmp_source2 : std_logic_vector(15 downto 0);
signal value1, value2 : std_logic_vector(31 downto 0);
type regsarray IS array (0 to 2**12-1) OF std_logic_vector(49 downto 0);
signal reg_file : regsarray;
signal tmp_nanoinstruction: std_logic_vector(49 downto 0);
signal rw: std_logic;
begin
reg_process:process(ck,reset)
begin
if reset='1' then
state<=1;
elsif rising_edge(ck) then
state<= next_state;
end if;
end process reg_process;
emphasized text
I don't understand what I'm doing wrong.
Thank you in advance.


I agree with Matthew Taylor: the architecture needs to be closed.
Try to add the following to the end of your file:
end asic_rtl;

Related

No feasible entry to subprogram shift_left, type error near

I am trying to use the function shift_left() in my project, but I'm getting 2 errors I can't explain:
Error: type error near 'shift left'; expected type 'std_logic_vector'
but temp IS a std_logic_vector!
Error: no feasible entry for subprogram 'shift_left' found
the signals used in the code are defined as:
signal shifted_pixel, temp : std_logic_vector(15 downto 0);
signal i_data : std_logic_vector(7 downto 0);
the snippet below is written within a process
temp <= "00000000" & i_data;
shifted_pixel <= shift_left(temp, 5);
full code below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity project is
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_start : in std_logic;
i_data : in std_logic_vector(7 downto 0);
);
end project;
architecture rtl of project is
signal shifted_pixel, temp : std_logic_vector(15 downto 0);
begin
process(i_data)
begin
temp <= "00000000" & i_data;
shifted_pixel <= shift_left(temp, 5);
end process;
end rtl;

The shift_left function in numeric_std package takes an unsigned as first argument and it returns an unsigned value.
So you have to cast your values:
shifted_pixel <= std_logic_vector(shift_left(unsigned(temp), 5));
HTH

VHDL getting a std_logic_vector out of an array of std_logic_vector

I have a Problem. I have an array of std_logic_vector and I input a value unsinged(3 downto 0) and I want to use value as the Index of the array.
So far so good but I should get a std_logic_vector out of the array and put in the Output segments (which is also a std_logic_vector with the same size) but I get the error:
> can't match type conversion with type array type "std_logic_vector"
here is my Code:
> library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity getarrayvalue is
port(
value : in unsigned(3 downto 0);
clk : in std_logic;
segments : out std_logic_vector(6 downto 0)
);
end entity;
architecture v1 of getarrayvalue is
type rom_type is array(0 to 9) of std_logic_vector(6 downto 0);
signal rom: rom_type :=("1111110","0110000","1101101","1111001","0110011","1011011","1011111","1110000","1111111","1111011");
signal val_i: integer;
val_i <= to_integer(value);
process(clk)
begin
if rising_edge(clk) then
segments <= rom_type(val_i);
end if;
end process;
end architecture;
Does anyone know how to fix this problem ? Thanks!

VHDL component output returns zeros

I'm writing something in VHDL about an essay and I'm facing a strange situation. I've written some components, simulated and tested them, and everything seems to works fine. However, when simulating the top entity, I'm getting zeros as a result! Please take a look at the following listings:
Top Entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity foobar is
port ( data_i : in std_logic_vector(39 downto 0);
sum_12bit_o : out std_logic_vector(11 downto 0)
);
end foobar;
architecture Behavioral of foobar is
--Declare components
component four_10bit_word_adder is
port( --Input signals
a_byte_in: in std_logic_vector(9 downto 0);
b_byte_in: in std_logic_vector(9 downto 0);
c_byte_in: in std_logic_vector(9 downto 0);
d_byte_in: in std_logic_vector(9 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(11 downto 0)
);
end component;
-- Signal declaration
signal int: std_logic_vector(11 downto 0);
signal intdata: std_logic_vector(39 downto 0);
begin
intdata <= data_i; --DEBUG
U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20),
intdata(19 downto 10), intdata(9 downto 0),
'0', int);
end Behavioral;
four_10bit_word_adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_10bit_word_adder is
generic (
bits: integer := 10
);
port( --Input signals
a_byte_in: in std_logic_vector(bits-1 downto 0);
b_byte_in: in std_logic_vector(bits-1 downto 0);
c_byte_in: in std_logic_vector(bits-1 downto 0);
d_byte_in: in std_logic_vector(bits-1 downto 0);
cin: in std_logic;
--Output signals
val12bit_out: out std_logic_vector(bits+1 downto 0)
);
end four_10bit_word_adder;
architecture Behavioral of four_10bit_word_adder is
-- Component Declaration
component compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end component;
--------------------------------------------------------+
component generic_11bit_adder
port (
A: in std_logic_vector(10 downto 0); --Input A
B: in std_logic_vector(10 downto 0); --Input B
CI: in std_logic; --Carry in
O: out std_logic_vector(10 downto 0); --Sum
CO: out std_logic --Carry Out
);
end component;
--------------------------------------------------------+
-- Declare internal signals
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal
signal byte_out: std_logic_vector(bits-1 downto 0);
signal carry: std_logic_vector(bits-1 downto 0);
signal int11bit: std_logic_vector(bits downto 0);
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder.
-- See the paper for more info.
signal Concat_A: std_logic_vector(bits downto 0);
signal Concat_B: std_logic_vector(bits downto 0);
signal co : std_logic;
begin
A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0),
c_byte_in(0), d_byte_in(0),
'0', int(0), byte_out(0), carry(0));
instances: for i in 1 to bits-1 generate
A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i),
c_byte_in(i), d_byte_in(i), int(i-1),
int(i), byte_out(i), carry(i));
end generate;
R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co);
Concat_A <= int(8) & byte_out;
Concat_B <= carry & '0';
process (co)
begin
if (co = '1') then
val12bit_out <= '1' & int11bit;
else
val12bit_out <= '0' & int11bit;
end if;
end process;
end Behavioral;
4:2 Compressor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compressor_4_2 is
port(a,b,c,d,cin : in std_logic;
cout, sum, carry : out std_logic
);
end compressor_4_2;
architecture Behavioral of compressor_4_2 is
-- Internal Signal Definitions
signal stage_1: std_logic;
begin
stage_1 <= d XOR (b XOR c);
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d));
sum <= (a XOR cin) XOR stage_1;
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1));
end Behavioral;
Generic 11-bit Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic_11bit_adder is
generic (
bits: integer := 11
);
port (
A: in std_logic_vector(bits-1 downto 0);
B: in std_logic_vector(bits-1 downto 0);
CI: in std_logic;
O: out std_logic_vector(bits-1 downto 0);
CO: out std_logic
);
end entity generic_11bit_adder;
architecture Behavioral of generic_11bit_adder is
begin
process(A,B,CI)
variable sum: integer;
-- Note: we have one bit more to store carry out value.
variable sum_vector: std_logic_vector(bits downto 0);
begin
-- Compute our integral sum, by converting all operands into integers.
sum := conv_integer(A) + conv_integer(B) + conv_integer(CI);
-- Now, convert back the integral sum into a std_logic_vector, of size bits+1
sum_vector := conv_std_logic_vector(sum, bits+1);
-- Assign outputs
O <= sum_vector(bits-1 downto 0);
CO <= sum_vector(bits); -- Carry is the most significant bit
end process;
end Behavioral;
I've tried a ton of things, but without any success. Do you have any idea what am I doing wrong? Sorry for the long question and thank you for your time.

Take a look at your process to generate val12bit_out in your four_10bit_word_adder entity. It's missing an input.
Also, there are several other issues. Fixing this one issue will not fix everything. But once you fix it, I think things will be a lot more clear.

Trying to understand simulation errors with Xilinx

I am getting some erros that I cant make sense and was hoping I could get some help.
ERROR: [VRFC 10-469] cannot update 'in' object shift_reg [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:25]
ERROR: [VRFC 10-925] indexed name is not a std_logic_vector [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:27]
ERROR: [VRFC 10-1504] unit simple_one_bit_serial_shift_register_behavior ignored due to previous errors [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:16]
INFO: [VRFC 10-240] VHDL file C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd ignored due to errors
I have tried altering the code to suit but nothing works ! this is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_one_bit_serial_shift_register is
port(
clk : in std_logic;
reset : in std_logic;
shift_in : in std_logic_vector(31 downto 0);
shift_reg : in std_logic_vector(1 downto 0);
shift_out : out std_logic_vector(31 downto 0)
);
end simple_one_bit_serial_shift_register;
architecture simple_one_bit_serial_shift_register_behavior of simple_one_bit_serial_shift_register is
begin
--signal shift_reg : std_logic_vector(31 downto 0);
--signal shift_in : std_logic;
--signal shift_out : std_logic;
process (clk)
begin
if rising_edge(clk) then
shift_reg <= shift_reg(30 downto 0) & shift_in;
end if;
shift_out <= shift_reg(31);
end process;
end simple_one_bit_serial_shift_register_behavior
;

In line 25 the input shift_reg port is assigned, using shift_reg <= ..., but it is not legal to assign to an input port.
In line 27 there is reference to bit 31 in shift_reg(31), but shift_reg only has index 1 and 0 in declaration with shift_reg : in std_logic_vector(1 downto 0);. And indexing a single bit like (31) has type std_logic, which does not match the std_logic_vector type of target shift_out.

Why is my Xilinx ISE Simulator crashing?

I am trying to make an ALU for floating point numbers.This is my code and whenever I try to run simulation of a testbench waveform simulator crashes stating this:
isim_beh.exe has stopped working
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fp is
port( in_one:in std_logic_vector(31 downto 0);
in_two:in std_logic_vector(31 downto 0);
select_line:in std_logic_vector(2 downto 0);
output:out std_logic_vector(31 downto 0));
end fp;
architecture Behavioral of fp is
signal bb:std_logic_vector(31 downto 0);
signal j,k,l:std_logic_vector(31 downto 0);
component floating
port (ina,inb:in std_logic_vector(31 downto 0);
sss:in std_logic_vector(2 downto 0);
outb:out std_logic_vector(31 downto 0));
end component;
component adder
port( a:in std_logic_vector(31 downto 0);
b:in std_logic_vector(31 downto 0);
sss:in std_logic_vector(2 downto 0);
oo:out std_logic_vector(31 downto 0));
end component;
begin
u1:floating port map(in_one,in_two,select_line,j); --When ss=10 then multiply is chosen
u2:adder port map(in_one,in_two,select_line,k); --When ss=00 then addition is chosen and when ss=01 then subtraction is chosen
output<=(not in_one) when select_line="100" else
(in_one and in_two) when select_line="101" else
(in_one or in_two) when select_line="110" else
j+k;
end Behavioral;
PS Floating is the component for multiplication. Adder is the component for addition and subtraction.

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