Finite State Machine in vhdl - vhdl

Question

For a project I'm making a PWM multiplexer but no succes with my FSM. When I receive an interrupt of PWM_INT the counter should increment or go to 0 if max is reached. The counter depends the state of the FSM.
This is my implementation:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PWM : in STD_LOGIC;
PWM_INT : in STD_LOGIC;
PWM_A : out STD_LOGIC;
PWM_B : out STD_LOGIC;
PWM_C : out STD_LOGIC);
end Mux;
architecture Behavioral of Mux is
type state is (iddle,state_1,state_2,state_3,state_4,state_5,state_6,new_fsm);
signal old_state : state ;
signal new_state : state ;
signal counter : integer range 6 downto 0;
begin
process(CLK)
begin
if RST = '1' then
counter <= 0;
PWM_A <= '0';
PWM_B <= '0';
PWM_C <= '0';
elsif CLK'event and CLK = '1' then
if PWM_INT = '1' then
if counter < 6 then
counter <= counter + 1;
else
counter <= 0;
end if;
end if;
end if;
end process;
----- Clocked Process FSM -----
process(CLK)
begin
if RST = '1' then
old_state <= iddle;
elsif (CLK'event and CLK = '1') then
old_state <= new_state;
end if;
end process;
----- Transitions -----
process(old_state,counter)
begin
case old_state is
when iddle => if counter = 0 then
new_state <= state_1;
else
new_state <= iddle;
end if;
when state_1 => if counter = 1 then
new_state <= state_2;
else
new_state <= state_1;
end if;
when state_2 => if counter = 2 then
new_state <= state_3;
else
new_state <= state_2;
end if;
when state_3 => if counter = 3 then
new_state <= state_4;
else
new_state <= state_3;
end if;
when state_4 => if counter = 4 then
new_state <= state_5;
else
new_state <= state_4;
end if;
when state_5 => if counter = 5 then
new_state <= state_6;
else
new_state <= state_5;
end if;
when state_6 => if counter = 6 then
new_state <= state_1;
else
new_state <= state_6;
end if;
when others => new_state <= iddle;
end case;
end process;
----- Output FSM -----
process(old_state)
begin
case old_state is
when iddle => PWM_A <= '0';
PWM_B <= '0';
PWM_C <= '0';
when state_1 => PWM_A <= PWM;
PWM_B <= '0';
PWM_C <= '0';
when state_2 => PWM_A <= PWM;
PWM_B <= '0';
PWM_C <= '0';
when state_3 => PWM_A <= '0';
PWM_B <= PWM;
PWM_C <= '0';
when state_4 => PWM_A <= '0';
PWM_B <= PWM;
PWM_C <= '0';
when state_5 => PWM_A <= '0';
PWM_B <= '0';
PWM_C <= PWM;
when state_6 => PWM_A <= '0';
PWM_B <= '0';
PWM_C <= PWM;
when others => PWM_A <= '0';
PWM_B <= '0';
PWM_C <= '0';
end case;
end process;
end Behavioral;
The testbench to test the program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TB_Mux is
end TB_Mux;
architecture Behavioral of TB_Mux is
component Mux
port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PWM : in STD_LOGIC;
PWM_INT : in STD_LOGIC;
PWM_A : out STD_LOGIC;
PWM_B : out STD_LOGIC;
PWM_C : out STD_LOGIC);
end component;
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal PWM : STD_LOGIC;
signal PWM_INT : STD_LOGIC;
signal PWM_A : STD_LOGIC;
signal PWM_B : STD_LOGIC;
signal PWM_C : STD_LOGIC;
constant CLK_Period : time:= 8 ns;
begin
u0:Mux
port map( CLK => CLK,
RST => RST,
PWM => PWM,
PWM_INT => PWM_INT,
PWM_A => PWM_A,
PWM_B => PWM_B,
PWM_C => PWM_C);
process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
process
begin
PWM <= '0';
RST <= '1';
PWM_INT <= '0';
wait for 5 * clk_period;
PWM <= '1';
RST <='0';
PWM_INT <='1';
wait for 1 * clk_period;
PWM_INT <= '0';
wait for 5 * clk_period;
PWM_INT <='1';
wait for 1 * clk_period;
PWM_INT <= '0';
wait for 5 * clk_period;
PWM_INT <='1';
wait for 1 * clk_period;
PWM_INT <= '0';
wait;
end process;
end Behavioral;
Thanks in advance!

Answer 1

Your sensitivity lists are incomplete.