I have 18 output and 9 push switches to work with and one led as output which changing its states each time the push button is pressed to automate the chance of two players. my code is not working, pls help
my code is...expected behavour is that when momentarily in1 switch is high then play_to_play should toggle on each event of the inputs and according to play_to_play status and in1 high either ou11 or ou21 should go high i.e one player has played his chance and automatically at the next event it takes that it is player 2 chance
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TicTac is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
in4 : in STD_LOGIC;
in5 : in STD_LOGIC;
in6 : in STD_LOGIC;
in7 : in STD_LOGIC;
in8 : in STD_LOGIC;
in9 : in STD_LOGIC;
reset : in STD_LOGIC;
p_to_play : out STD_Logic;
p1_win : out STD_LOGIC;
p2_win : out STD_LOGIC;
ou11 : out STD_LOGIC;
ou12 : out STD_LOGIC;
ou13 : out STD_LOGIC;
ou14 : out STD_LOGIC;
ou15 : out STD_LOGIC;
ou16 : out STD_LOGIC;
ou17 : out STD_LOGIC;
ou18 : out STD_LOGIC;
ou19 : out STD_LOGIC;
ou21 : out STD_LOGIC;
ou22 : out STD_LOGIC;
ou23 : out STD_LOGIC;
ou24 : out STD_LOGIC;
ou25 : out STD_LOGIC;
ou26 : out STD_LOGIC;
ou27 : out STD_LOGIC;
ou28 : out STD_LOGIC;
ou29 : out STD_LOGIC);
end TicTac;
architecture Behavioral of TicTac is
Signal temp1, temp2, temp3, temp4, temp5, temp6,temp7, temp8, temp9,p1_play :std_logic :='0';
signal o11,o12,o13,o14,o15,o16,o17,o18,o19,o21,o22,o23,o24,o25,o26,o27,o28,o29 :std_logic :='0';
signal p1win,p2win :std_logic :='0';
begin
process(in1,in2,in3,in4,in5,in6,in7,in8,in9,reset)
begin
if ((in1'event or in2'event or in3'event or in4'event or in5'event or in6'event or in7'event or in8'event or in9'event) and
(in1='1' or in2 ='1' or in3='1' or in4='1' or in5='1' or in6='1' or in7='1' or in8='1' or in9='1')) then
p1_play <= not(p1_play);
if(reset'event and reset= '1') then
temp1 <='0';
temp2 <='0';
temp3 <='0';
temp4 <='0';
temp5 <='0';
temp6 <='0';
temp7 <='0';
temp8 <='0';
temp9 <='0';
p1_play <= '0';
p1win <='0';
p2win <='0';
o11 <='0';
o12 <='0';
o13 <='0';
o14 <='0';
o15 <='0';
o16 <='0';
o17 <='0';
o18 <='0';
o19 <='0';
o21 <='0';
o22 <='0';
o23 <='0';
o24 <='0';
o25 <='0';
o26 <='0';
o27 <='0';
o28 <='0';
o29 <='0';
end if;
if(in1= '1') then
temp1 <='1';
end if;
if(in2= '1') then
temp2 <='1';
end if;
if(in3= '1') then
temp3 <='1';
end if;
if(in4= '1') then
temp1 <='1';
end if;
if(in5= '1') then
temp5 <='1';
end if;
if(in6= '1') then
temp6 <='1';
end if;
if(in7= '1') then
temp7 <='1';
end if;
if(in8= '1') then
temp8 <='1';
end if;
if(in9= '1') then
temp9 <='1';
end if;
if(p1_play='0' and temp1='1') then
o11 <= '1';
end if;
if(p1_play='0' and temp2='1') then
o12 <= '1';
end if;
if(p1_play='0' and temp3='1') then
o13 <= '1';
end if;
if(p1_play='0' and temp4='1') then
o14 <= '1';
end if;
if(p1_play='0' and temp5='1') then
o15 <= '1';
end if;
if(p1_play='0' and temp6='1') then
o16 <= '1';
end if;
if(p1_play='0' and temp7='1') then
o17 <= '1';
end if;
if(p1_play='0' and temp8='1') then
o18 <= '1';
end if;
if(p1_play='0' and temp9='1') then
o19 <= '1';
end if;
if(p1_play='1' and temp1='1') then
o21 <= '1';
end if;
if(p1_play='1' and temp2='1') then
o22 <= '1';
end if;
if(p1_play='1' and temp3='1') then
o23 <= '1';
end if;
if(p1_play='1' and temp4='1') then
o24 <= '1';
end if;
if(p1_play='1' and temp5='1') then
o25 <= '1';
end if;
if(p1_play='1' and temp6='1') then
o26 <= '1';
end if;
if(p1_play='1' and temp7='1') then
o27 <= '1';
end if;
if(p1_play='1' and temp8='1') then
o28 <= '1';
end if;
if(p1_play='1' and temp9='1') then
o29 <= '1';
end if;
if((o11='1' and o12='1' and o13='1') or (o14='1' and o15='1' and o16='1') or (o17='1' and o18='1' and o19='1')
or (o11='1' and o14='1' and o17='1') or (o12='1' and o15='1' and o18='1') or (o13='1' and o16='1' and o19='1')
or (o11='1' and o15='1' and o19='1') or (o13='1' and o15='1' and o17='1')) then
p1win <='1';
end if;
if((o21='1' and o22='1' and o23='1') or (o24='1' and o25='1' and o26='1') or (o27='1' and o28='1' and o29='1')
or (o21='1' and o24='1' and o27='1') or (o22='1' and o25='1' and o28='1') or (o23='1' and o26='1' and o29='1')
or (o21='1' and o25='1' and o29='1') or (o23='1' and o25='1' and o27='1')) then
p2win <='1';
end if;
end if;
end process;
ou11 <= o11;
ou12 <= o12;
ou13 <= o13;
ou14 <= o14;
ou15 <= o15;
ou16 <= o16;
ou17 <= o17;
ou18 <= o18;
ou19 <= o19;
ou21 <= o21;
ou22 <= o22;
ou23 <= o23;
ou24 <= o24;
ou25 <= o25;
ou26 <= o26;
ou27 <= o27;
ou28 <= o28;
ou29 <= o29;
p_to_play <= p1_play;
p1_win <= p1win;
p2_win <= p2win;
end Behavior
al;
Processes in VHDL are not the same as processes on a regular programming language. All signal assignments within a process actually occur at the time the process completes (actually a delta time later, which is basically a 0 time difference). Since you are trying to use the value of temp that you just assigned earlier in the process, but it hasn't actually been written yet, you are not triggering your if statement until the next time the process runs.
As an aside, I didn't notice any mechanism to prevent players from playing in spaces that they or their opponent already played.
EDIT: Also, what do you plan to do with this? If you want to put it on a real FPGA with real switches it likely won't work because of an electromechanical phenomenon called switch bouncing that makes each press of a switch seem like many to the hardware.
EDIT2: To fix this (still won't fix switch bouncing) you may want to scrap temp entirely (replacing it with the "in" signals) and put the entire contents of the process, except the reset stuff, inside your if statement that detects rising edges on the in signals.
EDIT3: Here is a VHDL model for a 4x4 tic-tac-toe board with your hardware setup expanded to the 16 squares of a 4x4 board. See if you can understand what is done and why, then adapt it to a 3x3 board.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TicTac is
Port (button : in std_logic_vector(16 downto 1);
reset : in std_logic;
p_to_play : out std_logic;
p1_win : out std_logic := '0';
p2_win : out std_logic := '0';
ou1 : out std_logic_vector(16 downto 1);
ou2 : out std_logic_vector(16 downto 1));
end TicTac;
architecture Behavioral of TicTac is
signal o1 : std_logic_vector(16 downto 1) := (others => '0');
signal o2 : std_logic_vector(16 downto 1) := (others => '0');
signal o : std_logic_vector(16 downto 1) := (others => '0');
signal p : std_logic;
signal win : std_logic;
signal win1 : std_logic;
signal win2 : std_logic;
begin
ou1 <= o1;
ou2 <= o2;
p_to_play <= p;
p1_win <= win1;
p2_win <= win2;
win <= win1 or win2;
gen_spots : for i in 1 to 16 generate --3 flip flops share a clock (button) for every space on the board
process(button(i), reset)
begin
if(reset = '1') then
o(i) <= '0';
o1(i) <= '0';
o2(i) <= '0';
elsif(button(i)'event and button(i)='1' and o(i)='0' and win='0') then
o(i) <= '1';
if (p = '0') then
o1(i) <= '1';
else
o2(i) <= '1';
end if;
end if;
end process;
end generate gen_spots;
process(o) --determines current player by xoring the o values together.
variable ot : std_logic;
begin
ot := '0';
for i in 1 to 16 loop
ot := ot xor o(i);
end loop;
p <= ot;
end process;
process(o1) --checks if player 1 wins
begin
win1 <= '0'; --only happens if none of the win1 <= '1' statements occur
for i in 0 to 3 loop
if (o1(1+i*4)='1' and o1(2+i*4)='1' and o1(3+i*4)='1' and o1(4+i*4)='1') then --rows
win1 <= '1';
end if;
if (o1(1+i)='1' and o1(5+i)='1' and o1(9+i)='1' and o1(13+i)='1') then --columns
win1 <= '1';
end if;
end loop;
if (o1(1)='1' and o1(6)='1' and o1(11)='1' and o1(16)='1') or (o1(4)='1' and o1(7)='1' and o1(10)='1' and o1(13)='1') then --diagonals
win1 <= '1';
end if;
end process;
process(o2) --checks if player 2 wins
begin
win2 <= '0'; --only happens if none of the win2 <= '1' statements occur
for i in 0 to 3 loop
if (o2(1+i*4)='1' and o2(2+i*4)='1' and o2(3+i*4)='1' and o2(4+i*4)='1') then --rows
win2 <= '1';
end if;
if (o2(1+i)='1' and o2(5+i)='1' and o2(9+i)='1' and o2(13+i)='1') then --columns
win2 <= '1';
end if;
end loop;
if (o2(1)='1' and o2(6)='1' and o2(11)='1' and o2(16)='1') or (o2(4)='1' and o2(7)='1' and o2(10)='1' and o2(13)='1') then --diagonals
win2 <= '1';
end if;
end process;
end Behavioral;
I haven't done exhaustive tests, but this compiles and works for a couple test cases.
Please remember to mark this as the correct answer if it solved your problem.
----------------------------------------------------------------------------------
----------------------------- TICTAC TOE GAME ------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cs_main is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
in4 : in STD_LOGIC;
in5 : in STD_LOGIC;
in6 : in STD_LOGIC;
in7 : in STD_LOGIC;
in8 : in STD_LOGIC;
in9 : in STD_LOGIC;
output1 : out STD_LOGIC_VECTOR (8 downto 0);
output2 : out STD_LOGIC_VECTOR (8 downto 0);
chance_real : out STD_LOGIC;
wing : out STD_LOGIC;
winr : out STD_LOGIC;
reset : in STD_LOGIC);
end cs_main;
architecture Behavioral of cs_main is
signal temp1,out1,out2,out11,out22 :std_logic_vector (8 downto 0):= "000000000";
signal chance : std_logic := '0';
signal wing1,winr1 : std_logic := '0';
begin
tictac :process(in1,in2,in3,in4,in5,in6,in7,in8,in9)
begin
if rising_edge (reset) then
out1 <= "000000000";
out2 <= "000000000";
chance <= '0';
wing1 <= '0';
winr1 <= '0';
else
if (wing1 = '0' and winr1 = '0') then
if rising_edge (in1) then
if (chance = '0') then
out1 <= "000000001";
elsif(chance = '1') then
out2 <= "000000001";
end if;
chance <= not chance ;
elsif rising_edge(in2) then
if (chance = '0') then
out1 <= "000000010";
elsif(chance = '1') then
out2 <= "000000010";
end if;
chance <= not chance ;
elsif rising_edge(in3) then
if (chance = '0') then
out1 <= "000000100";
elsif(chance = '1') then
out2 <= "000000100";
end if;
chance <= not chance ;
elsif rising_edge(in4) then
if (chance = '0') then
out1 <= "000001000";
elsif(chance = '1') then
out2 <= "000001000";
end if;
chance <= not chance ;
elsif rising_edge(in5) then
if (chance = '0') then
out1 <= "000010000";
elsif(chance = '1') then
out2 <= "000010000";
end if;
chance <= not chance ;
elsif rising_edge(in6) then
if (chance = '0') then
out1 <= "000100000";
elsif(chance = '1') then
out2 <= "000100000";
end if;
chance <= not chance ;
elsif rising_edge(in7) then
if (chance = '0') then
out1 <= "001000000";
elsif(chance = '1') then
out2 <= "001000000";
end if;
chance <= not chance ;
elsif rising_edge(in8) then
if (chance = '0') then
out1 <= "010000000";
elsif(chance = '1') then
out2 <= "010000000";
end if;
chance <= not chance ;
elsif rising_edge(in9) then
if (chance = '0') then
out1 <= "100000000";
elsif(chance = '1') then
out2 <= "100000000";
end if;
chance <= not chance ;
end if;
end if;
out11 <= out11 or out1;
out22 <= out22 or out2;
if(((out11 = "000000111" or out11 = "000111000" or out11 = "111000000" or
out11 = "001001001" or out11 = "010010010" or out11 = "100100100" or
out11 = "100010001" or out11 = "001010100" ) and chance ='0') or
((out22 = "000000111" or out22 = "000111000" or out22 = "111000000" or
out22 = "001001001" or out22 = "010010010" or out22 = "100100100" or
out22 = "100010001" or out22 = "001010100" ) and chance = '1')) then
if (chance = '0')then
wing1 <= '1';
winr1 <= '0';
elsif (chance = '1') then
wing1 <= '0';
winr1 <= '1';
end if;
else
wing1 <= '0';
winr1 <= '0';
end if;
end if;
end process tictac;
output1 <= out11 ;
output2 <= out22 ;
chance_real <= chance;
wing <= wing1;
winr <= winr1;
end Behavioral;
The code compiled without an error on my QUARTUS II version 15 software. i programmed it on my ALTERA DE2 FPGA BOARD but it does not display on the monitor. can anyone tell me what to do please
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TicTac is
Port (button : in std_logic_vector(16 downto 1);
reset : in std_logic;
p_to_play : out std_logic;
p1_win : out std_logic := '0';
p2_win : out std_logic := '0';
ou1 : out std_logic_vector(16 downto 1);
ou2 : out std_logic_vector(16 downto 1));
end TicTac;
architecture Behavioral of TicTac is
signal o1 : std_logic_vector(16 downto 1) := (others => '0');
signal o2 : std_logic_vector(16 downto 1) := (others => '0');
signal o : std_logic_vector(16 downto 1) := (others => '0');
signal p : std_logic;
signal win : std_logic;
signal win1 : std_logic;
signal win2 : std_logic;
begin
ou1 <= o1;
ou2 <= o2;
p_to_play <= p;
p1_win <= win1;
p2_win <= win2;
win <= win1 or win2;
gen_spots : for i in 1 to 16 generate --3 flip flops share a clock (button) for every space on the board
process(button(i), reset)
begin
if(reset = '1') then
o(i) <= '0';
o1(i) <= '0';
o2(i) <= '0';
elsif(button(i)'event and button(i)='1' and o(i)='0' and win='0') then
o(i) <= '1';
if (p = '0') then
o1(i) <= '1';
else
o2(i) <= '1';
end if;
end if;
end process;
end generate gen_spots;
process(o) --determines current player by xoring the o values together.
variable ot : std_logic;
begin
ot := '0';
for i in 1 to 16 loop
ot := ot xor o(i);
end loop;
p <= ot;
end process;
process(o1) --checks if player 1 wins
begin
win1 <= '0'; --only happens if none of the win1 <= '1' statements occur
for i in 0 to 3 loop
if (o1(1+i*4)='1' and o1(2+i*4)='1' and o1(3+i*4)='1' and o1(4+i*4)='1') then --rows
win1 <= '1';
end if;
if (o1(1+i)='1' and o1(5+i)='1' and o1(9+i)='1' and o1(13+i)='1') then --columns
win1 <= '1';
end if;
end loop;
if (o1(1)='1' and o1(6)='1' and o1(11)='1' and o1(16)='1') or (o1(4)='1' and o1(7)='1' and o1(10)='1' and o1(13)='1') then --diagonals
win1 <= '1';
end if;
end process;
process(o2) --checks if player 2 wins
begin
win2 <= '0'; --only happens if none of the win2 <= '1' statements occur
for i in 0 to 3 loop
if (o2(1+i*4)='1' and o2(2+i*4)='1' and o2(3+i*4)='1' and o2(4+i*4)='1') then --rows
win2 <= '1';
end if;
if (o2(1+i)='1' and o2(5+i)='1' and o2(9+i)='1' and o2(13+i)='1') then --columns
win2 <= '1';
end if;
end loop;
if (o2(1)='1' and o2(6)='1' and o2(11)='1' and o2(16)='1') or (o2(4)='1' and o2(7)='1' and o2(10)='1' and o2(13)='1') then --diagonals
win2 <= '1';
end if;
end process;
end Behavioral;
Related
I am trying to write a program to detect if a given input is a prime number or not. When I run the test bench I get correct results however when I run it on the FPGA it only recognizes numbers that are divisible 3 or even as not prime. Any number such as 25 which is divisible by 5 will result in isPrime being 1. What could be causing this inconsistent result?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
entity PrimeNumber is
Port ( clk: in std_logic;
rst : in std_logic;
input: in std_logic_vector(15 downto 0);
isPrime: out std_logic:= '0';
testOut: out std_logic_vector(31 downto 0)
);
end PrimeNumber;
architecture Behavioral of PrimeNumber is
SIGNAL current_state: std_logic_vector(2 downto 0);
signal next_state: std_logic_vector(2 downto 0):= "000";
signal max: integer;
signal temp: integer;
signal x: integer;
signal nextX:integer;
signal localPrime : std_logic:= '0';
signal current : integer;
signal update: std_logic := '0';
begin
nextX <= x +2;
process(current_state,input)
begin
case (current_state) is
when "000" => --Initial State
update <= '0';
localPrime <= '0';
if(input < x"0004")then
next_state <= "111";
else
max <= to_integer(unsigned(input(15 downto 1)));
current <=to_integer(unsigned(input));
if(input(0) = '0')then
next_state <= "110";
else
next_state <= "001";
end if;
end if;
when "001" => -- Computation State
localPrime <= '0';
temp <= current mod x;
if(x > max) then
next_state <= "111";
else
next_state <= "010";
end if;
update <= '1';
when "010" => -- Checking State
update <= '0';
localPrime <= '0';
if(temp = 0) then
next_state <= "110";
else
next_state <= "001";
end if;
when "110" =>
localPrime <= '0'; -- Not Prime State
next_state <= "110";
when "111" =>
update <= '0';
localPrime <= '1'; --Prime State
next_state <= "111";
when others =>
temp <= 0;
localPrime <= '0';
next_state <= "000";
end case;
end process;
Update_Registers: process(clk)
begin
if(clk'event and clk = '1') then
if ( rst = '1') then
current_state <= "000";
isPrime <= '0';
x<=3;
else
if(update = '1') then
x <= nextX;
end if;
current_state <= next_state;
isPrime <= localPrime;
end if;
end if;
end process;
end Behavioral;
To quickly check sim/syn mismatch, with the visibility you need outside of HW: output the mod result to a port, sim, should still "work"... syn, compile your (hopefully, verilog) netlist for TB, point to compiled netlist, sim, check the mod result against RTL/expected results.
I'm newbie in FPGAs and VHDL. This time, I m trying to send Data from FPGA to TTL. I' m using GPIO pins for TX and GND and Data can be changed with switch on FPGA. My issue is whenever i press the button on FPGA, I always see FF on terminal. I couldn't find where the problem is.
Here is TX code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_Tx is
port(
CLK : in std_logic;
Reset : in std_logic;
Button : in std_logic;
Data : in std_logic_vector(7 downto 0);
Out_Tx : out std_logic
);
end entity;
Architecture Behavioral of UART_Tx is
constant Baudrate : integer := 9600;
constant CLK_Hiz : integer := 50000000;
constant CLK_Bit : integer := (CLK_Hiz / Baudrate) + 1;
signal tx_Data_ind : integer range 0 to 7;
signal counter_baud : integer range 0 to (CLK_Bit - 1) := 0;
signal shift_button : std_logic_vector (3 downto 0) := (others => '0');
signal button_out : std_ulogic := '1';
signal baud_pulse : std_ulogic := '0';
signal tx_enable : std_ulogic := '0';
signal tx_Data : std_logic_vector (7 downto 0) := (others => '0');
signal tx_cikis : std_ulogic;
signal tx_tamam : std_ulogic := '0';
signal counter_sil : std_ulogic := '0';
begin
process(CLK, Reset)
begin
if (Reset = '0') then
baud_pulse <= '0';
counter_baud <= 0;
elsif (rising_edge(CLK)) then
if (counter_baud < (CLK_Bit - 1)) then
counter_baud <= counter_baud + 1;
baud_pulse <= '0';
else
counter_baud <= 0;
baud_pulse <= '1';
end if;
if (counter_sil = '1') then
counter_baud <= 0;
end if;
end if;
end process;
process(CLK, Reset)
begin
if (Reset = '0') then
tx_Data <= (others => '0');
tx_data_ind <= 0;
tx_enable <= '0';
elsif (rising_edge(CLK)) then
tx_cikis <= '1';
out_tx <= tx_cikis;
shift_button(3) <= button;
shift_button(2 downto 0) <= shift_button(3 downto 1);
if shift_button(3 downto 0) = "001" then
button_out <= '0';
end if;
if (button_out = '0') then
counter_sil <= '1';
tx_cikis <= '0';
if (tx_cikis = '0') then
tx_enable <= '1';
end if;
if (tx_enable = '1') then
counter_sil <= '0';
tx_Data <= Data;
if (baud_pulse = '1') then
tx_cikis <= tx_Data(tx_Data_ind);
if (tx_data_ind < 7) then
tx_Data_ind <= tx_Data_ind + 1;
else
tx_tamam <= '1';
end if;
if (tx_tamam = '1') then
tx_Data <= (others => '0');
tx_Data_ind <= 0;
tx_enable <= '0';
button_out <= '1';
tx_cikis <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
end Architecture;
Here is Testbench code:
library ieee;
use ieee.std_logic_1164.all;
entity tb_UART_Tx is
end tb_UART_Tx;
architecture tb of tb_UART_Tx is
component UART_Tx
port (CLK : in std_logic;
Reset : in std_logic;
Button : in std_logic;
Data : in std_logic_vector (7 downto 0);
Out_Tx : out std_logic);
end component;
signal CLK : std_logic:='0';
signal Reset : std_logic:='1';
signal Button : std_logic:='1';
signal Data : std_logic_vector (7 downto 0);
signal Out_Tx : std_logic;
constant TbPeriod : time := 20 ns;
signal TbSimEnded : std_logic := '0';
begin
dut : UART_Tx
port map (CLK => CLK,
Reset => Reset,
Button => Button,
Data => Data,
Out_Tx => Out_Tx);
clk_process: process
begin
CLK <= '0';
wait for TbPeriod/2;
CLK <= '1';
wait for TbPeriod/2;
end process;
stimuli : process
begin
Reset <= '0';
wait for 20 ns;
Button <= '1';
Data <= "00110000";
wait for 30 ns;
Button <= '0';
wait for 50 ns;
Button <= '1';
wait for 1000 ns;
-- Button <= '0';
-- wait for 30 ns;
-- Button <= '1';
TbSimEnded <= '1';
wait;
end process;
end tb;
configuration cfg_tb_UART_Tx of tb_UART_Tx is
for tb
end for;
end cfg_tb_UART_Tx;
Added Testbench results
EDIT: HERE is the working code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_Tx is
port(
CLK: in std_logic;
nReset: in std_logic;
nButton: in std_logic;
Data: in std_logic_vector (7 downto 0);
Data_Tx: out std_logic
);
end UART_Tx;
architecture Behavioral of UART_Tx is
constant Baudrate: integer:= 9600;
constant CLK_Hiz: integer:= 50000000;
constant CLK_Bit: integer:= (CLK_Hiz / Baudrate) + 1;
signal tx_counter: integer range 1 to 9:= 1;
signal counter_baud: integer range 0 to (CLK_Bit - 1):= 0;
signal shift_nButton:std_logic_vector (3 downto 0):= (others => '1');
signal tx_reg: std_logic_vector (7 downto 0):= (others => '0');
signal nButton_out: std_ulogic:= '1';
signal baud_pulse: std_ulogic;
signal tx_out: std_ulogic:= '1';
signal counter_del: std_ulogic;
signal start_bit: std_ulogic:='0';
signal data_bit: std_ulogic:='0';
signal stop_bit: std_ulogic:='0';
begin
process(CLK,nReset)
begin
if(nReset = '0') then
baud_pulse <= '0';
counter_baud <= 0;
elsif(rising_edge(CLK)) then
if(counter_baud < (CLK_Bit - 1)) then
counter_baud <= counter_baud + 1;
baud_pulse <= '0';
else
counter_baud <= 0;
baud_pulse <= '1';
end if;
if(counter_del = '1') then
counter_baud <= 0;
end if;
end if;
end process;
process(CLK, nReset)
begin
Data_Tx <= tx_out;
if(nReset = '0') then
tx_reg <= (others => '0');
tx_counter <= 1;
elsif(rising_edge(CLK)) then
shift_nButton(3) <= nButton;
shift_nButton(2 downto 0) <= shift_nButton(3 downto 1);
if shift_nButton(2 downto 0) = "001" then
nButton_out <= '0';
counter_del <= '1';
start_bit <= '1';
end if;
if(nButton_out = '1') then
tx_out <= '1';
elsif(nButton_out = '0') then
counter_del <= '0';
if(start_bit = '1') then
tx_out <= '0';
tx_reg <= Data;
if(baud_pulse = '1') then
start_bit <= '0';
data_bit <= '1';
end if;
end if;
if(data_bit = '1')then
if(tx_counter > 0 and tx_counter < 10) then
tx_out <= tx_reg((tx_counter)-1);
if(baud_pulse = '1') then
tx_counter <= tx_counter + 1;
if(tx_counter = 9)then
data_bit <= '0';
stop_bit <= '1';
end if;
end if;
end if;
end if;
if(stop_bit = '1') then
tx_out <= '1';
tx_counter <= 1;
if(baud_pulse = '1') then
stop_bit <= '0';
nButton_out <= '1';
tx_reg <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end Behavioral;
i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such mistake.
i try to operate on flags to have multiple signal drivers on bus but there's just something not right. The multiple drivers are on scl, sda, start_clk and stop_clk. Is it because those flags are for example in two different processes?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2C_com is
port (
reset_en: in std_logic;
clk: in std_logic;
sda: inout std_logic;
scl: out std_logic;
RD:in std_logic;
WR: in std_logic;
addr: buffer std_logic_vector(7 downto 0)
);
end I2C_com;
architecture MAIN of I2C_com is
signal data :std_logic_vector (12 downto 0):="0000000000010";
signal i2c_clk: std_logic ;
signal clk_count : unsigned(19 downto 0):="00000000000000000100";
type program_state is (start,init,error_rd_wr,slave,ack);
signal state: program_state;
signal write_data: std_logic_vector (7 downto 0):=(others => '0');
signal read_data: std_logic_vector (7 downto 0):=(others => '0');
signal clk_enable: std_logic;
signal reset: std_logic:='1';
signal start_clk: std_logic:= 'Z';
signal stop_clk: std_logic:= 'Z';
signal strech: std_logic := '0';
signal cnt_addr: integer := 0;
signal ack_error: std_logic;
signal sda_data: std_logic;
signal start_data: std_logic:= 'Z';
begin
i2c_clock: process(clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
elsif falling_edge(clk) then
if clk_count < unsigned(data) then
clk_count <= clk_count + 1;
clk_enable <= '1';
else
clk_count <= x"00000";
clk_enable <= '0';
end if;
i2c_clk <= clk_enable;
if start_clk = '1' then
sda <= '0';
scl <= '0';
start_clk <= '0';
end if;
if stop_clk = '1' then
sda <= '0';
scl <= '0';
stop_clk <= '0';
end if;
end if;
end process i2c_clock;
--
process(i2c_clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
reset <= '0';
cnt_addr <= 0;
state <= init;
elsif rising_edge(i2c_clk) then
case state is
when init =>
if RD = '1' or WR = '1' then
state <= start;
else
state <= error_rd_wr;
end if;
when start =>
start_clk <= '1';
state <= slave;
when slave =>
start_data <= '1';
if cnt_addr < 8 then
sda_data <= addr(cnt_addr);
cnt_addr <= cnt_addr + 1;
else
cnt_addr <= 0;
state <= ack;
end if;
when error_rd_wr =>
reset <= '1';
when ack =>
start_data <= '0';
ack_error <= sda;
if ack_error = '1' then
stop_clk <= '1';
reset <= '1';
else
end if;
if RD = '1' then
elsif WR = '1' then
else
stop_clk <= '1';
reset <= '1';
end if;
end case;
end if;
end process;
sda <= sda_data when start_data = '1' else 'Z';
scl <= i2c_clk when start_clk = '0' and stop_clk = '0' else 'Z';
end MAIN;
A signal for synthesis can be driven from only one process or one continuous assign; for simulation multiple drivers are possible using resolved signals like std_logic.
The scl and sda are driven both from the i2c_clock process and the continuous assign in the end of the file.
The start_clk and stop_clk are driven both from the i2c_clock process and the other unnamed process.
One possibility for scl and sda is to only drive these from the continuous assign, since synthesis tools often prefer tri-state output to be written like:
q <= value when en = '1' else 'Z';
I am a newbie when it comes to VHDL, but i am working on a counter than can manually count up and down by the push of a button.. Somehow i am only getting this error, and i dunno what i am doing wrong, all other checks are good. any suggestion?
This is the error i get:
ERROR:Xst:827 - line 101: Signal s2 cannot be synthesized, bad synchronous description.
The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
entity updown is Port (
rst : in STD_LOGIC;
plus , plusin: in STD_LOGIC;
minus, minusin : in STD_LOGIC;
clk : in STD_LOGIC;
ud_out, ud_out2 : out STD_LOGIC_VECTOR (3 downto 0)
);
end updown;
architecture Behavioral of updown is
signal s : unsigned (3 downto 0):= "0000";
signal s2 : unsigned (3 downto 0) := "0000";
begin
process(rst, plus, minus, clk, plusin, minusin)
begin
if rst='1' then
s <= "0000";
s2 <= "0000";
else
if rising_edge (clk) then
if plus ='1' or plusin = '1' then
if s = "1001" then
s <= "0000";
if s2 = "1001" then
s2 <= "0000";
else
s2 <= s2 + 1;
end if;
else
s <= s + 1;
end if;
end if;
else
if minus ='1' or minusin = '1' then
if s = "0000" then
s <= "1001";
if s2= "0000" then
s2 <= "1001";
else
s2 <= s2 - 1;
end if;
else
s <= s - 1;
end if;
end if;
end if;
end if;
end process;
ud_out <= std_logic_vector(s);
ud_out2 <= std_logic_vector(s2);
end Behavioral;
Your description of a synchronous process is flawed. A synchronous process has events that update only on the edge of a clock signal (although in this case there is an also an asynchronous reset behaviour )
Your sensitivity list contains more than it needs to describe a synchronous process.
Replace
process(rst, plus, minus, clk, plusin, minusin)
with
process(rst, clk )
signals will then only update when the clock transisitions, or rst changes.
Some compilers are even more picky, and might require you to change
else if rising_edge (clk)then
to
elsif rising_edge(clk) then
EDIT:
This should work. I've layed it out clearly so its actually easy to follow what's going on. I'd suggest you do the same in future. It make simple closure errors easy to spot
entity updown is
port (
signal clk : in std_logic;
signal rst : in std_logic;
signal plus : in std_logic;
signal plusin : in std_logic;
signal minus : in std_logic;
signal minusin : in std_logic;
signal ud_out : out std_logic_vector(3 downto 0);
signal ud_out2 : out std_logic_vector(3 downto 0)
);
end entity updown;
architecture behavioral of updown is
signal s : unsigned (3 downto 0);
signal s2 : unsigned (3 downto 0);
begin
p_counter_process: process(rst, clk)
begin
if rst ='1' then
s <= (others => '0');
s2 <= (others => '0');
elsif rising_edge(clk) then
if plus ='1' or plusin = '1' then
if s = "1001" then
s <= "0000";
if s2 = "1001" then
s2 <= "0000";
else
s2 <= s2 + 1;
end if;
else
s <= s +1;
end if;
end if;
-- you had a mismatched end if statement here. Removed
if minus ='1' or minusin = '1' then
if s = "0000" then
s <= "1001";
if s2= "0000" then
s2 <= "1001";
else
s2 <= s2 - 1;
end if;
else
s <= s - 1;
end if;
end if;
end if;
end process;
ud_out <= std_logic_vector(s);
ud_out2 <= std_logic_vector(s2);
end architecture;
I am new to VHDL. I need to write a module to do filtering of data. My module structure is:
a_rst - async reset
clk - clock
s_rst - sync reset
valid_in - 0 - no data, 1 - where is data
data_in - [7 downto 0]
Out signals:
valid_out - 0 - no data, 1 - where is data
data_out - [7 downto 0]
I write testbeanch which puts to data_in of my module: 00,01,02,03,0A,02,00,01,02,0F.
But my module returns: 00,01,AA,03,0A,02,00,01,AA,0F
insted of: 00,01,AA,03,0A,02,00,01,02,0F.
I tried to do this:
--libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--entity
entity ex6_v03 is
port
(
a_rst : in std_logic;
clk : in std_logic; -- 200 MHz
s_rst : in std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector (7 downto 0);
valid_out : out std_logic;
data_out : out std_logic_vector (7 downto 0)
);
end entity ex6_v03;
architecture behavior of ex6_v03 is
signal st : integer := 0;
begin
process(a_rst, clk)
begin
-- asynchronous reset
if (a_rst = '1') then
data_out <= x"00";
valid_out <= '0';
-- synchronous reset
elsif rising_edge(clk) then -- clk
if (s_rst = '1') then
valid_out <= '0';
data_out <= x"00";
else
-- normal activity
if(valid_in = '1') then
-- main logic
if(data_in = x"00") then
st <= 1;
valid_out <= '1';
data_out <= data_in;
elsif(st = 1 and data_in = x"01") then
st <= 2;
valid_out <= '1';
data_out <= data_in;
elsif(st = 2 and data_in = x"02") then
st <= 3;
valid_out <= '1';
data_out <= x"AA";
elsif(st = 3 and data_in = x"03") then
valid_out <= '1';
data_out <= data_in;
st <= 0;
else
st <= 0;
valid_out <= '1';
data_out <= data_in;
end if;
-- end main logic
else
valid_out <= '0';
data_out <= x"00";
end if;
end if;
end if;
end process;
end architecture behavior;
But my module do not wait for 0x03 and instantly sends 0xAA. How to fix this?
You need to add a 1 clock cycle buffer so you know if the next input is 03 before you choose whether to send 02 or AA. Of course, this means the output wont appear until 2 cycles after the input instead of only one. See revised code:
--libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--entity
entity ex6_v03 is
port
(
a_rst : in std_logic;
clk : in std_logic; -- 200 MHz
s_rst : in std_logic;
valid_in : in std_logic;
data_in : in std_logic_vector (7 downto 0);
valid_out : out std_logic;
data_out : out std_logic_vector (7 downto 0)
);
end entity ex6_v03;
architecture behavior of ex6_v03 is
signal st : integer := 0;
signal bvalid : std_logic := '0'; --is buffer valid?
signal data_buffer : std_logic_vector (7 downto 0); --data from previous cycle
begin
process(a_rst, clk)
begin
if (a_rst = '1') then -- asynchronous reset
data_out <= x"00";
valid_out <= '0';
bvalid <= '0';
elsif rising_edge(clk) then -- clk
if (s_rst = '1') then --sync reset
valid_out <= '0';
bvalid <= '0';
data_out <= x"00";
else -- normal activity
if(valid_in = '1') then --fill buffer
if(data_in = x"00") then
st <= 1;
data_out <= data_in;
elsif(st = 1 and data_in = x"01") then
st <= 2;
data_out <= data_in;
elsif(st = 2 and data_in = x"02") then
st <= 3;
else
st <= 0;
end if;
data_buffer <= data_in;
bvalid <= '1';
else
bvalid <= '0';
end if;
if(bvalid = '1') then --use buffer to populate output
valid_out <= '1'
if(st = 3 and data_in = x"03" and valid_in = '1') then --EDIT: make sure the x"03" sitting on the input is actually valid
data_out <= x"AA"; --output for the previous cycle (buffer contains x"02")
else
data_out <= data_buffer;
end if
else
valid_out <= '0';
data_out <= x"00";
end if;
end if;
end if;
end process;
end architecture behavior;