Tic-tac-toe in VHDL - vhdl

Question

I am writing VHDL code of Tic-tac-toe game. In my code, winning state is delayed one turn.
(P.S. I am not very familiar with clock so, I have to set p1_play and p2_play value i.e. 1 or 0 using force in waveform). Can someone please suggest me what makes my program to delay 1 turn.
Thanks you.
(clickable)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tttt1 is
Port (
in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
in3 : in STD_LOGIC;
in4 : in STD_LOGIC;
in5 : in STD_LOGIC;
in6 : in STD_LOGIC;
in7 : in STD_LOGIC;
in8 : in STD_LOGIC;
in9 : in STD_LOGIC;
p1_play : in STD_LOGIC;
p2_play : in STD_LOGIC;
p1_win : out STD_LOGIC;
p2_win : out STD_LOGIC;
out_11 : out STD_LOGIC;
out_12 : out STD_LOGIC;
out_13 : out STD_LOGIC;
out_21 : out STD_LOGIC;
out_22 : out STD_LOGIC;
out_23 : out STD_LOGIC;
out_31 : out STD_LOGIC;
out_32 : out STD_LOGIC;
out_33 : out STD_LOGIC);
end entity tttt1;
architecture Behavioral of tttt1 is
signal temp11, temp12, temp13, temp14, temp15, temp16, temp17, temp18, temp19, temp21, temp22, temp23, temp24, temp25, temp26, temp27, temp28, temp29 :std_logic :='0';
signal p1win,p2win :std_logic :='0';
signal o11,o12,o13,o21,o22,o23,o31,o32,o33:std_logic :='0';
begin
process(in1,in2,in3,in4,in5,in6,in7,in8,in9)
begin
-----------Start Player 1 Play-------------
if(p1_play ='1' and p2_play='0') then
if (in1= '1') then
temp11 <='1';
temp21 <='0';
o11<='1';
elsif(in2= '1') then
temp12 <='1';
temp22 <='0';
o12<='1';
elsif(in3= '1') then
temp13 <='1';
temp23 <='0';
o13<='1';
elsif(in4= '1') then
temp14 <='1';
temp24 <='0';
o21<='1';
elsif(in5= '1') then
temp15 <='1';
temp25 <='0';
o22<='1';
elsif(in6= '1') then
temp16 <='1';
temp26 <='0';
o23<='1';
elsif(in7= '1') then
temp17 <='1';
temp27 <='0';
o31<='1';
elsif(in8= '1') then
temp18 <='1';
temp28 <='0';
o32<='1';
elsif(in9= '1') then
temp19 <='1';
temp29 <='0';
o33<='1';
end if;
end if;
if ((temp11='1' and temp12='1' and temp13='1') or (temp14='1' and temp15='1' and temp16='1') or (temp17='1' and temp18='1' and temp19='1')
or (temp11='1' and temp14='1' and temp17='1') or (temp12='1' and temp15='1' and temp18='1') or (temp13='1' and temp16='1' and temp19='1')
or (temp11='1' and temp15='1' and temp19='1') or (temp13='1' and temp15='1' and temp17='1')) then
p1win<='1';
end if;
---------------End Player 1 Play---------------
--------------Start Player 2 Play--------------
if(p2_play ='1' and p1_play='0') then
if (in1= '1')then
temp21 <='1';
temp11 <='0';
o11<='1';
elsif(in2= '1') then
temp22 <='1';
temp12 <='0';
o12<='1';
elsif(in3= '1') then
temp23 <='1';
temp13 <='0';
o13<='1';
elsif(in4= '1') then
temp24 <='1';
temp14 <='0';
o21<='1';
elsif(in5= '1') then
temp25 <='1';
temp15 <='0';
o22<='1';
elsif(in6= '1') then
temp26 <='1';
temp16 <='0';
o23<='1';
elsif(in7= '1') then
temp27 <='1';
temp17 <='0';
o31<='1';
elsif(in8= '1') then
temp28 <='1';
temp18 <='0';
o32<='1';
elsif(in9= '1') then
temp29 <='1';
temp19 <='0';
o33<='1';
end if;
end if;
if( (temp21='1' and temp22='1' and temp23='1') or (temp24='1' and temp25='1' and temp26='1') or (temp27='1' and temp28='1' and temp29='1')
or (temp21='1' and temp24='1' and temp27='1') or (temp22='1' and temp25='1' and temp28='1') or (temp23='1' and temp26='1' and temp29='1')
or (temp21='1' and temp25='1' and temp29='1') or (temp23='1' and temp25='1' and temp27='1')) then
p2win<='1';
end if;
---------------End Player 2 Play---------------
end process;
p1_win <= p1win;
p2_win <= p2win;
out_11 <= o11;
out_12 <= o12;
out_13 <= o13;
out_21 <= o21;
out_22 <= o22;
out_23 <= o23;
out_31 <= o31;
out_32 <= o32;
out_33 <= o33;
end Behavioral;

Answer 1

The cause of your delay on seeing p2_win is that temp11 through temp13, temp21 through temp 23 and temp31 through temp33 are not in the process sensitivity list (nor should they be). The update of p1_win or p2_win doesn't occur until there's an event on signal in the process sensitivity list, in this case a transistion on in3 and in9.
Making the assignments to the two win outputs separate concurrent signal assigments gets the delay right:
The modified code (With formatting for readability) looks like:
library ieee;
use ieee.std_logic_1164.all;
entity tttt1 is
port (
in1: in std_logic;
in2: in std_logic;
in3: in std_logic;
in4: in std_logic;
in5: in std_logic;
in6: in std_logic;
in7: in std_logic;
in8: in std_logic;
in9: in std_logic;
p1_play: in std_logic;
p2_play: in std_logic;
p1_win: out std_logic;
p2_win: out std_logic;
out_11: out std_logic;
out_12: out std_logic;
out_13: out std_logic;
out_21: out std_logic;
out_22: out std_logic;
out_23: out std_logic;
out_31: out std_logic;
out_32: out std_logic;
out_33: out std_logic
);
end entity tttt1;
architecture behavioral of tttt1 is
signal temp11, temp12,
temp13, temp14,
temp15, temp16,
temp17, temp18,
temp19, temp21,
temp22, temp23,
temp24, temp25,
temp26, temp27,
temp28, temp29: std_logic := '0';
signal p1win,p2win: std_logic := '0';
signal o11,o12,o13,o21,
o22,o23,o31,o32,
o33: std_logic := '0';
begin
process (in1,in2,in3,in4,in5,in6,in7,in8,in9)
begin
-----------Start Player 1 Play-------------
if p1_play = '1' and p2_play = '0' then
if in1 = '1' then
temp11 <= '1';
temp21 <= '0';
o11 <= '1';
elsif in2 = '1' then
temp12 <= '1';
temp22 <= '0';
o12 <= '1';
elsif in3 = '1' then
temp13 <= '1';
temp23 <= '0';
o13 <= '1';
elsif in4 = '1' then
temp14 <= '1';
temp24 <= '0';
o21 <= '1';
elsif in5 = '1' then
temp15 <= '1';
temp25 <= '0';
o22 <= '1';
elsif in6 = '1' then
temp16 <= '1';
temp26 <= '0';
o23<= '1';
elsif in7 = '1' then
temp17 <= '1';
temp27 <= '0';
o31<= '1';
elsif in8 = '1' then
temp18 <= '1';
temp28 <= '0';
o32 <= '1';
elsif in9 = '1' then
temp19 <= '1';
temp29 <= '0';
o33 <= '1';
end if;
end if;
-- if (temp11 = '1' and temp12 = '1' and temp13 = '1') or
-- (temp14 = '1' and temp15 = '1' and temp16 = '1') or
-- (temp17 = '1' and temp18 = '1' and temp19 = '1') or
-- (temp11 = '1' and temp14 = '1' and temp17 = '1') or
-- (temp12 = '1' and temp15 = '1' and temp18 = '1') or
-- (temp13 = '1' and temp16 = '1' and temp19 = '1') or
-- (temp11 = '1' and temp15 = '1' and temp19 = '1') or
-- (temp13 = '1' and temp15 = '1' and temp17 = '1') then
--
-- p1win <= '1';
--
-- end if;
---------------End Player 1 Play---------------
--------------Start Player 2 Play--------------
if p2_play = '1' and p1_play = '0' then
if in1 = '1' then
temp21 <= '1';
temp11 <= '0';
o11 <= '1';
elsif in2 = '1' then
temp22 <= '1';
temp12 <= '0';
o12 <= '1';
elsif in3 = '1' then
temp23 <= '1';
temp13 <= '0';
o13 <= '1';
elsif in4 = '1' then
temp24 <= '1';
temp14 <= '0';
o21 <= '1';
elsif in5 = '1' then
temp25 <= '1';
temp15 <= '0';
o22 <= '1';
elsif in6 = '1' then
temp26 <= '1';
temp16 <= '0';
o23 <= '1';
elsif in7 = '1' then
temp27 <= '1';
temp17 <= '0';
o31 <= '1';
elsif in8 = '1' then
temp28 <= '1';
temp18 <= '0';
o32 <= '1';
elsif in9 = '1' then
temp29 <= '1';
temp19 <= '0';
o33 <= '1';
end if;
end if;
-- if (temp21 = '1' and temp22 = '1' and temp23 = '1') or
-- (temp24 = '1' and temp25 = '1' and temp26 = '1') or
-- (temp27 = '1' and temp28 = '1' and temp29 = '1') or
-- (temp21 = '1' and temp24 = '1' and temp27 = '1') or
-- (temp22 = '1' and temp25 = '1' and temp28 = '1') or
-- (temp23 = '1' and temp26 = '1' and temp29 = '1') or
-- (temp21 = '1' and temp25 = '1' and temp29 = '1') or
-- (temp23 = '1' and temp25 = '1' and temp27 = '1') then
--
-- p2win <= '1';
--
-- end if;
---------------End Player 2 Play---------------
end process;
p1win <= (temp11 and temp12 and temp13) or
(temp14 and temp15 and temp16) or
(temp17 and temp18 and temp19) or
(temp11 and temp14 and temp17) or
(temp12 and temp15 and temp18) or
(temp13 and temp16 and temp19) or
(temp11 and temp15 and temp19) or
(temp13 and temp15 and temp17);
p2win <= (temp21 and temp22 and temp23) or
(temp24 and temp25 and temp26) or
(temp27 and temp28 and temp29) or
(temp21 and temp24 and temp27) or
(temp22 and temp25 and temp28) or
(temp23 and temp26 and temp29) or
(temp21 and temp25 and temp29) or
(temp23 and temp25 and temp27);
p1_win <= p1win;
p2_win <= p2win;
out_11 <= o11;
out_12 <= o12;
out_13 <= o13;
out_21 <= o21;
out_22 <= o22;
out_23 <= o23;
out_31 <= o31;
out_32 <= o32;
out_33 <= o33;
end architecture behavioral;
The functional changes are limited to making the win output assignments concurrent signal assignment statements.
A test bench was used to reproduce the stimuli in your linked waveform:
library ieee;
use ieee.std_logic_1164.all;
entity tttt1_tb is
end entity;
architecture foo of tttt1_tb is
signal in1: std_logic := '0';
signal in2: std_logic := '0';
signal in3: std_logic := '0';
signal in4: std_logic := '0';
signal in5: std_logic := '0';
signal in6: std_logic := '0';
signal in7: std_logic := '0';
signal in8: std_logic := '0';
signal in9: std_logic := '0';
signal p1_play: std_logic := '0';
signal p2_play: std_logic := '0';
signal p1_win: std_logic;
signal p2_win: std_logic;
signal out_11: std_logic;
signal out_12: std_logic;
signal out_13: std_logic;
signal out_21: std_logic;
signal out_22: std_logic;
signal out_23: std_logic;
signal out_31: std_logic;
signal out_32: std_logic;
signal out_33: std_logic;
begin
DUT:
entity work.tttt1
port map (
in1 => in1,
in2 => in2,
in3 => in3,
in4 => in4,
in5 => in5,
in6 => in6,
in7 => in7,
in8 => in8,
in9 => in9,
p1_play => p1_play,
p2_play => p2_play,
p1_win => p1_win,
p2_win => p2_win,
out_11 => out_11,
out_12 => out_12,
out_13 => out_13,
out_21 => out_21,
out_22 => out_22,
out_23 => out_23,
out_31 => out_31,
out_32 => out_32,
out_33 => out_33
);
STIMULI:
process
begin
in1 <= '1';
p1_play <= '1';
wait for 100 ns;
in1 <= '0';
in2 <= '1';
p1_play <= '0';
p2_play <= '1';
wait for 100 ns;
in2 <= '0';
in9 <= '1';
p1_play <= '1';
p2_play <= '0';
wait for 100 ns;
in5 <= '1';
in9 <= '0';
p1_play <= '0';
p2_play <= '1';
wait for 100 ns;
in5 <= '0';
in7 <= '1';
p1_play <= '1';
p2_play <= '0';
wait for 100 ns;
in7 <= '0';
in8 <= '1';
p1_play <= '0';
p2_play <= '1';
wait for 100 ns;
in3 <= '1';
in8 <= '0';
p1_play <= '1';
p2_play <= '0';
wait for 100 ns;
wait;
end process;
end architecture;
There's a missing rule check to not allow a player to capture a square obliviously. That rule should be implemented as well as a method for clearing a game. The game state is held in inferred latches, that might be more widely synthesis eligible if the latches were describe in separate process driven by a single input. There would also be an expectation that the inputs are debounced.
Because there'd be a hardware expectation that an input occurs while the value of p1_play and p2_play is stable, it is possible to use a clock and pass input events (one clock in duration). It used to be common to have these sorts of games describe asynchronously in hardware implementations (think '70s and '80s).