Hello can somebody help me with something thats been bugging me for a while. I have a simple case statement and to the best of my knowledge the syntax is good. see the below code
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY D7SEGSEL IS
PORT (
SW :in std_logic_vector(3 DOWNTO 0);
SEG :out std_logic_vector(6 DOWNTO 0)
);
END ENTITY D7SEGSEL;
ARCHITECTURE behavioral OF D7SEGSEL IS
BEGIN
CASE SW IS
WHEN "1000000" => SEG <= "0000";
"1111001" => SEG <= "0001";
"0100100" => SEG <= "0010";
"0110000" => SEG <= "0011";
"0011001" => SEG <= "0100";
"0010010" => SEG <= "0101";
"0000010" => SEG <= "0110";
"1111000" => SEG <= "0111";
"0000000" => SEG <= "1000";
"0011000" => SEG <= "1001";
"0001000" => SEG <= "1010";
"0000011" => SEG <= "1011";
"1000110" => SEG <= "1100";
"0100001" => SEG <= "1101";
"0000110" => SEG <= "1110";
"0001110" => SEG <= "1111";
END CASE;
END ARCHITECTURE behavioral;
its for a simple 7SEG LED driver, each time i compile the code though I get the following error messages:
Error (10500): VHDL syntax error at D7SEGCASE.vhd(19) near text
"CASE"; expecting "end", or "(", or an identifier ("case" is a
reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at D7SEGCASE.vhd(21) near text "=>"; expecting > "(", or
"'", or "."
Can anyone point out the obvious in what I'm doing wrong
I have already made a decoder for the 7seg with a select/when statement but want to practice the use of case and then make it synchronous with the addition of a clock input
You have a few problems.
You are missing your process statement.
You are missing subsequent "when" after your first condition.
You have reversed your condition and your assignment in your WHEN conditions.
See fixes below:
ARCHITECTURE behavioral OF D7SEGSEL IS
BEGIN
my_case : process(sw, seg)
begin
CASE SW IS
WHEN "0000" => SEG <= "1000000";
WHEN "0001" => SEG <= "1111001";
-- Other Assignments follow...
END CASE;
end process my_case;
END ARCHITECTURE behavioral;
As pointed out by others, there are some problems with your code, but luckily there are different options to implement what you want.
Case (process)
process (SW) is
begin
case SW is
when "0000" => SEG <= "1000000";
when "0001" => SEG <= "1111001";
when "0010" => SEG <= "0100100";
when "0011" => SEG <= "0110000";
when "0100" => SEG <= "0011001";
when "0101" => SEG <= "0010010";
when "0110" => SEG <= "0000010";
when "0111" => SEG <= "1111000";
when "1000" => SEG <= "0000000";
when "1001" => SEG <= "0011000";
when "1010" => SEG <= "0001000";
when "1011" => SEG <= "0000011";
when "1100" => SEG <= "1000110";
when "1101" => SEG <= "0100001";
when "1110" => SEG <= "0000110";
when "1111" => SEG <= "0001110";
when others => SEG <= (others => 'X');
end case;
end process;
When (concurrent)
SEG <= "1000000" when SW = "0000" else
"1111001" when SW = "0001" else
"0100100" when SW = "0010" else
"0110000" when SW = "0011" else
"0011001" when SW = "0100" else
"0010010" when SW = "0101" else
"0000010" when SW = "0110" else
"1111000" when SW = "0111" else
"0000000" when SW = "1000" else
"0011000" when SW = "1001" else
"0001000" when SW = "1010" else
"0000011" when SW = "1011" else
"1000110" when SW = "1100" else
"0100001" when SW = "1101" else
"0000110" when SW = "1110" else
"0001110" when SW = "1111" else
(others => 'X');
Select (concurrent)
d7seg : with SW select
SEG <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0011000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when "1111",
(others => 'X') when others;
The Select (concurrent) is compact and with few repetitions, and is likely to yield a small implementation, so will be a good choice.
I can't see process in your code.
process(sw,seg)
.
.
.
end process
check if you get after adding it
Related
I have a 4x3 keypad, i wrote this FSM for interfacing it with my Nexys2 board, trouble I am having here is
When I run the code, the LEDs glow without any key pressed, it shows random combinations automatically
When I press a key it shows that particular combination then goes on to the next condition of ROW without any key pressed. And sometimes it does not even respond if i press a key.
What is happening? What is wrong with this code? I am clueless. Can someone point out the mistakes and suggest some solution? Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity keypad_3x4 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ROW : in STD_LOGIC_VECTOR (3 downto 0);
COL : out STD_LOGIC_VECTOR (2 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0)
);
end keypad_3x4;
architecture Behavioral of keypad_3x4 is
architecture Behavioral of keypad_3x4 is
TYPE STATE_TYPE is
( RESET_ST,
S1,
S2,
S3,
S4,
S5,
S6
);
signal state: STATE_TYPE;
begin
process (CLK, RESET)
begin
if (RESET = '1') then
state <= RESET_ST;
elsif (CLK'event and CLK = '1') then
case (state) is
WHEN RESET_ST =>
LED <= (others => '0');
COL <= (others => '0');
state <= S1;
WHEN S1 =>
COL <= "001"; --C1 selected
LED <= (others => '0');
state <= S2;
WHEN S2 =>
if ROW <= "0001" then
led <= "0001"; --1
elsif ROW <= "0010" then
led <= "0100"; --4
elsif ROW <= "0100" then
led <= "0111"; --7
elsif ROW <= "1000" then
led <= "1111"; --*
else
LED <= (others => '0');
state <= S3;
end if;
WHEN S3 =>
COL <= "010"; --C2 selected
LED <= (others => '0');
state <= S4;
WHEN S4 =>
if ROW <= "0001" then
led <= "0010"; --2
elsif ROW <= "0010" then
led <= "0101"; --5
elsif ROW <= "0100" then
led <= "1000"; --8
elsif ROW <= "1000" then
led <= "0000"; --0
else
LED <= (others => '0');
state <= S5;
end if;
WHEN S5 =>
COL <= "100"; --C3 selected
LED <= (others => '0');
state <= S6;
WHEN S6 =>
if ROW <= "0001" then
led <= "0011"; --3
elsif ROW <= "0010" then
led <= "0110"; --6
elsif ROW <= "0100" then
led <= "1001"; --9
elsif ROW <= "1000" then
led <= "1111"; --#
else
LED <= (others => '0');
state <= RESET_ST;
end if;
WHEN others =>
state <= RESET_ST;
END case;
END if;
END process;
end Behavioral;
This code selects either the leds or the 7 segment display to show it's 8-bit data that i feed in through the switches. I select the led or the 7 segment through a push button. When I try to run it on my nexys2 board the led part works fine but as i press the pushbutton the selected 7segment glows and changes its value with the led glowing as well. Also the 7 segment changes it's value only when i press the pushbuton again. I am a newbie and i think I am having trouble making a good logic or what is the issue? any help would be appreciated!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity selector is
Port ( clk: in STD_LOGIC;
sel : in STD_LOGIC;
comb : in STD_LOGIC_VECTOR (7 downto 0);
segment : out STD_LOGIC_VECTOR (3 downto 0);
number : out STD_LOGIC_VECTOR (6 downto 0);
led: out STD_LOGIC_VECTOR (7 downto 0));
end selector;
architecture Behavioral of selector is
begin
process (clk, comb, sel) begin
if (clk'event and clk = '1') then
if sel = '1' then
segment <= "1110";
case (comb) is
when "00000000" => number <= "0000001"; --0
when "00000001" => number <= "1001111"; --1
when "00000010" => number <= "0010010"; --2
when "00000011" => number <= "0000110"; --3
when "00000100" => number <= "1001100"; --4
when "00000101" => number <= "0100100"; --5
when "00000110" => number <= "0100000"; --6
when "00000111" => number <= "0001111"; --7
when "00001000" => number <= "0000000"; --8
when "00001001" => number <= "0000100"; --9
when others => number <= "1111111"; -- off
end case;
elsif sel = '0' then
case (comb) is
when "00000000" => led <= "00000000"; --0
when "00000001" => led <= "00000001"; --1
when "00000010" => led <= "00000011"; --2
when "00000011" => led <= "00000111"; --3
when "00000100" => led <= "00001111"; --4
when "00000101" => led <= "00011111"; --5
when "00000110" => led <= "00111111"; --6
when "00000111" => led <= "01111111"; --7
when "00001000" => led <= "11111111"; --8
when others => led <= "00000000"; -- off
end case;
end if;
end if;
end process;
end Behavioral;
You are not changing the value for the output that is not selected, so it remains in the state it has been assigned last.
Also, your code your code will only ever have an effect on the rising edge of the clock, so the sensitivity list can be reduced to (clk) (at which point, clk'event is implied).
Here is my code for writing two decimal numbers on 7 segment. I have used AN0 and AN1. I am getting this really weird error I don't know how to resolve it, is there any problem with my case structure? What does this error mean? any help would be appreciated
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity twosegments is
Port ( clk : in STD_LOGIC;
dig0: in std_logic_vector (3 downto 0);
dig1: in STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (3 downto 0));
end twosegments;
architecture Behavioral of twosegments is
constant prescaler: STD_LOGIC_VECTOR(16 downto 0) := "00000000110010000";
signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal sel: STD_LOGIC_VECTOR (1 downto 0);
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
process (clk) begin
if (clk'event and clk = '1') then
prescaler_counter <= prescaler_counter + 1;
if(prescaler_counter = prescaler) then
sel <= sel+1;
prescaler_counter <= (others => '0');
end if;
end if;
end process;
process (sel, dig0,dig1) begin
case sel is
when "00" => r_anode <= "1110";
when "01" => r_anode <= "1101";
--when "10" => r_anode <= "1110";
--when "11" => r_anode <= "1101";
when others => r_anode <= "1111";
end case;
case r_anode is
when "1110" => case "dig0" is
when "0000" => segment <= "0000001"; --0
when "0001" => segment <= "1001111"; --1
when "0010" => segment <= "0010010"; --2
when "0011" => segment <= "0000110"; --3
when "0100" => segment <= "1001100"; --4
when "0101" => segment <= "0100100"; --5
when "0110" => segment <= "0100000"; --6
when "0111" => segment <= "0001111"; --7
when "1000" => segment <= "0000000"; --8
when "1001" => segment <= "0000100"; --9
when others => segment <= "1111111";
end case;
when "1101" => case "dig1" is
when "0000" => segment <= "0000001"; --0
when "0001" => segment <= "1001111"; --1
when "0010" => segment <= "0010010"; --2
when "0011" => segment <= "0000110"; --3
when "0100" => segment <= "1001100"; --4
when "0101" => segment <= "0100100"; --5
when "0110" => segment <= "0100000"; --6
when "0111" => segment <= "0001111"; --7
when "1000" => segment <= "0000000"; --8
when "1001" => segment <= "0000100"; --9
when others => segment <= "1111111"; --off
end case;
when others => segment <= "1111111";
end case;
end process;
end Behavioral;
This is the weird error
FATAL_ERROR:HDLParsers:vhpcstr.c:2040:$Id: vhpcstr.c,v 1.64 2008/12/03 00:28:13 sandeepd Exp $:200 - INTERNAL ERROR... while parsing "E:/Xilinx Projects/twosegs/twosegments.vhd" line 62. Contact your hot line. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
There is a syntax error with quotes around dig0 and dig1 signal identifiers, so try to change case "dig0" is to case dig0 is, and case "dig1" is to case dig1 is.
But anyway, the Xilinx parser is not robust enough since it crashes, so it is a good habit to create a WebCase for issues like this, so Xilinx can improve in the future.
I would follow the error message directions. Specifically:
For technical support on this issue, please open a WebCase with this
project attached at http://www.xilinx.com/support
Iam making the code for a secuential tail lights for a mustang, but iam getting a latch with Llights and Rlights. According to my logic there should be no problem.
----------------------------------------------------------------------------------
-- Company: Pony incorporated
-- Engineer: Pony
--
-- Create Date: 17:41:27 10/23/2013
-- Design Name:
-- Module Name: Mustang_FSM - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 (Nexys 3 Digilent board)
-- Tool versions: ISE Webpack v14.6
-- Description: Using a Moore FSM, define the sequential tail
-- lights found on a Ford Mustang. Look at the
-- following video:
-- https://www.youtube.com/watch?v=KVFA-HuikfY
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: The realization of the Moore FSM is based
-- on the template described by your teacher
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mustang_FSM is
Port ( Lturn : in STD_LOGIC;
Rturn : in STD_LOGIC;
Hazard : in STD_LOGIC;
Rst : in STD_LOGIC;
Break : in STD_LOGIC;
Clk100MHz : in STD_LOGIC;
Llights : out STD_LOGIC_VECTOR (2 downto 0);
Rlights : out STD_LOGIC_VECTOR (0 to 2));
end Mustang_FSM;
architecture Behavioral of Mustang_FSM is
-- Definition of embedded signals and constants
-- Constants used for frequency division
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 4; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
-- Signal used by the frequency division process
signal Cont : integer range 0 to CtaMax;
signal Clk_En : STD_LOGIC;
-- State definition for the FSM
-- Binary encoding (default) will be used
-- Equivalent of enumeration types in programming languages
type state_values is (ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7, ST8);
signal pres_state, next_state: state_values;
-- One hot state coding
-- ONE HOT ENCODED state machine: Sreg0
-- subtype Sreg0_type is std_logic_vector(7 downto 0);
-- constant ST0: Sreg0_type := "00000001";
-- constant ST1: Sreg0_type := "00000010";
-- constant ST2: Sreg0_type := "00000100";
-- constant ST3: Sreg0_type := "00001000";
-- constant ST4: Sreg0_type := "00010000";
-- constant ST5: Sreg0_type := "00100000";
-- constant ST6: Sreg0_type := "01000000";
-- constant ST7: Sreg0_type := "10000000";
-- signal pres_state, next_state: Sreg0_type;
-- Used to concatenate Lturn, Rturn and Hazard for easier
-- handling
signal LRH : STD_LOGIC_VECTOR (3 downto 0);
begin
-- Frequency divider to obtain a 2Hz signal from
-- the 100 MHz board oscillator
FreqDiv: process (Rst, Clk100MHz)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk100MHz)) then
if Cont = CtaMax - 1 then
Cont <= 0;
Clk_En <= '1';
else
Cont <= Cont + 1;
Clk_En <= '0';
end if;
end if;
end process FreqDiv;
-- The FSM definition begins next
-- "Current State Register" (StateReg) description
StateReg: process (Clk100MHz,Clk_En,Rst)
begin
if (Rst = '1') then
pres_state <= ST0;
elsif (rising_edge(Clk100MHz) and Clk_En = '1') then
pres_state <= next_state;
end if;
end process StateReg;
-- "Next State Logic" (FSM) description
LRH <= Break & Lturn & Rturn & Hazard;
FSM: process (pres_state, LRH)
begin
case pres_state is
when ST0 =>
case LRH is
when "0000" => next_state <= ST0; -- All off
when "0110" => next_state <= ST0; -- All off
when "0100" => next_state <= ST2; -- Left Turn
when "0010" => next_state <= ST5; -- Right Turn
when "1000" => next_state <= ST8; -- Break
when others => next_state <= ST1; -- Hazard
end case;
when ST1 => next_state <= ST0;
when ST2 => next_state <= ST3;
when ST3 => next_state <= ST4;
when ST4 => next_state <= ST0;
when ST5 => next_state <= ST6;
when ST6 => next_state <= ST7;
when ST7 => next_state <= ST0;
when ST8 =>
case LRH is
when "1000" => next_state <= ST8;
when others => next_state <= ST0;
end case;
-- Include when others to avoid latches
when others => next_state <= ST0;
end case;
end process FSM;
-- "Output Logic" (Outputs) description
Outputs: process (pres_state)
begin
case pres_state is
when ST0 => Llights <= "000"; Rlights <= "000";
when ST1 => Llights <= "111"; Rlights <= "111";
when ST2 => Llights <= "001"; Rlights <= "000";
when ST3 => Llights <= "011"; Rlights <= "000";
when ST4 => Llights <= "111"; Rlights <= "000";
when ST5 => Llights <= "000"; Rlights <= "001";
when ST6 => Llights <= "000"; Rlights <= "011";
when ST7 => Llights <= "000"; Rlights <= "111";
when ST8 => Llights <= "111"; Rlights <= "111";
when others => null;
end case;
end process Outputs;
end Behavioral;
The description of the warning:
WARNING:Xst:737 - Found 3-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 3-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Thanks for the help. :D
Instead of this:
Outputs: process (pres_state)
begin
case pres_state is
when ST0 => Llights <= "000"; Rlights <= "000";
when ST1 => Llights <= "111"; Rlights <= "111";
when ST2 => Llights <= "001"; Rlights <= "000";
when ST3 => Llights <= "011"; Rlights <= "000";
when ST4 => Llights <= "111"; Rlights <= "000";
when ST5 => Llights <= "000"; Rlights <= "001";
when ST6 => Llights <= "000"; Rlights <= "011";
when ST7 => Llights <= "000"; Rlights <= "111";
when ST8 => Llights <= "111"; Rlights <= "111";
when others => null;
end case;
end process Outputs;
Do This:
Outputs: process (pres_state)
begin
case pres_state is
when ST0 => Llights <= "000"; Rlights <= "000";
when ST1 => Llights <= "111"; Rlights <= "111";
when ST2 => Llights <= "001"; Rlights <= "000";
when ST3 => Llights <= "011"; Rlights <= "000";
when ST4 => Llights <= "111"; Rlights <= "000";
when ST5 => Llights <= "000"; Rlights <= "001";
when ST6 => Llights <= "000"; Rlights <= "011";
when ST7 => Llights <= "000"; Rlights <= "111";
when ST8 => Llights <= "111"; Rlights <= "111";
when others => Llights <= "000"; Rlights <= "000";
end case;
end process Outputs;
The question your compiler is asking you is: "What is the value of Llights when pres_state is ST9?" I'm aware that ST9 doesn't exist, but the compiler doesn't care. Which is annoying.
Do not use a case statement inside a combinational process. If you add a clock to your output process it will work. Or you can use a VHDL SELECT signal assignment. The case statement inside the combinational process is generating the latch.
You could solve it like this: (this will add 1 clock cycle delay)
Outputs: process (Clk100MHz)
begin
if (rising_edge(Clk100MHz) then
case pres_state is
when ST0 => Llights <= "000"; Rlights <= "000";
when ST1 => Llights <= "111"; Rlights <= "111";
when ST2 => Llights <= "001"; Rlights <= "000";
when ST3 => Llights <= "011"; Rlights <= "000";
when ST4 => Llights <= "111"; Rlights <= "000";
when ST5 => Llights <= "000"; Rlights <= "001";
when ST6 => Llights <= "000"; Rlights <= "011";
when ST7 => Llights <= "000"; Rlights <= "111";
when ST8 => Llights <= "111"; Rlights <= "111";
when others => null;
end case;
end if;
end process Outputs;
You could also do this:
Llights <= "000" when pres_state = ST0 else
"111" when pres_state = ST1 else
etc etc
Or you can use a VHDL select signal assignment.
Is it possible to write a code segment and call it, instead of writing that segment many times? Ie. I want to reuse a segment of code as shown below:
process (currentState)
begin
case currentState is
when requiredCoinsTensAnode => anodes <= "100000";--turn on the tens display
case tensCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
nextState <= requiredCoinsUnitsAnode;--just displayed the tens digit, next we need to display the units digit
when requiredCoinsUnitsAnode => anodes <= "010000";--turn on the units display
case unitsCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
nextState <= insertedCoinsTensAnode;
end case;
end process;
Functions are one option, as ravi has pointed out.
function f_segDisplay (
signal segCount : std_logic_vector(6 downto 0))
return std_logic_vector(3 downto 0) is
begin -- f_segDisplay
case segCount is
when "0000" => return "1111110"; --0
when "0001" => return "0110000"; --1
when "0010" => return "1101101"; --2
when "0011" => return "1111001"; --3
when "0100" => return "0110011"; --4
when "0101" => return "1011011"; --5
when "0110" => return "1011111"; --6
when "0111" => return "1110000"; --7
when "1000" => return "1111111"; --8
when others => return "1111011"; --9
end case;
end f_segDisplay;
process (currentState, tensCount, unitsCount)
begin
case currentState is
when requiredCoinsTensAnode =>
anodes <= "100000"; --turn on the tens display
segDisplay <= f_segDisplay(tensCount);
nextState <= requiredCoinsUnitsAnode;
when requiredCoinsUnitsAnode =>
anodes <= "010000"; --turn on the units display
segDisplay <= f_segDisplay(unitsCount);
nextState <= insertedCoinsTensAnode;
end case;
end process;
Depending on the compiler and options, it may decide to put the function code in-line. This would cause multiple instances of the logic to be placed, much like your original code.
An alternative is that you take the common code out into another process:
p_segdisplay : process (segCount)
begin -- process p_segdisplay
case segCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
end process p_segdisplay;
process (currentState, tensCount, unitsCount)
begin
case currentState is
when requiredCoinsTensAnode =>
anodes <= "100000"; --turn on the tens display
segCount <= tensCount;
nextState <= requiredCoinsUnitsAnode;
when requiredCoinsUnitsAnode =>
anodes <= "010000"; --turn on the units display
segCount <= unitsCount;
nextState <= insertedCoinsTensAnode;
end case;
end process;
BTW: You need tensCount and unitsCount in your sensitivity list.
Abstracting a common resource like this is a useful technique when doing area or power concious designs.
Both should work in the same way, and perfect tools would produce the same logic from the two, but we rarely have perfect tools. Experiment with different styles. Some produce better results on some tools, some on others.
Yes, you can use functions in VHDL.
check http://www.csee.umbc.edu/portal/help/VHDL/design.html#funcd
http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_3.htm
That code is probably best in a function or procedure.
An entity is another way to encapsulate code in VHDL.