Here is my code for writing two decimal numbers on 7 segment. I have used AN0 and AN1. I am getting this really weird error I don't know how to resolve it, is there any problem with my case structure? What does this error mean? any help would be appreciated
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity twosegments is
Port ( clk : in STD_LOGIC;
dig0: in std_logic_vector (3 downto 0);
dig1: in STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (3 downto 0));
end twosegments;
architecture Behavioral of twosegments is
constant prescaler: STD_LOGIC_VECTOR(16 downto 0) := "00000000110010000";
signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others => '0');
signal sel: STD_LOGIC_VECTOR (1 downto 0);
signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
begin
anode <= r_anode;
process (clk) begin
if (clk'event and clk = '1') then
prescaler_counter <= prescaler_counter + 1;
if(prescaler_counter = prescaler) then
sel <= sel+1;
prescaler_counter <= (others => '0');
end if;
end if;
end process;
process (sel, dig0,dig1) begin
case sel is
when "00" => r_anode <= "1110";
when "01" => r_anode <= "1101";
--when "10" => r_anode <= "1110";
--when "11" => r_anode <= "1101";
when others => r_anode <= "1111";
end case;
case r_anode is
when "1110" => case "dig0" is
when "0000" => segment <= "0000001"; --0
when "0001" => segment <= "1001111"; --1
when "0010" => segment <= "0010010"; --2
when "0011" => segment <= "0000110"; --3
when "0100" => segment <= "1001100"; --4
when "0101" => segment <= "0100100"; --5
when "0110" => segment <= "0100000"; --6
when "0111" => segment <= "0001111"; --7
when "1000" => segment <= "0000000"; --8
when "1001" => segment <= "0000100"; --9
when others => segment <= "1111111";
end case;
when "1101" => case "dig1" is
when "0000" => segment <= "0000001"; --0
when "0001" => segment <= "1001111"; --1
when "0010" => segment <= "0010010"; --2
when "0011" => segment <= "0000110"; --3
when "0100" => segment <= "1001100"; --4
when "0101" => segment <= "0100100"; --5
when "0110" => segment <= "0100000"; --6
when "0111" => segment <= "0001111"; --7
when "1000" => segment <= "0000000"; --8
when "1001" => segment <= "0000100"; --9
when others => segment <= "1111111"; --off
end case;
when others => segment <= "1111111";
end case;
end process;
end Behavioral;
This is the weird error
FATAL_ERROR:HDLParsers:vhpcstr.c:2040:$Id: vhpcstr.c,v 1.64 2008/12/03 00:28:13 sandeepd Exp $:200 - INTERNAL ERROR... while parsing "E:/Xilinx Projects/twosegs/twosegments.vhd" line 62. Contact your hot line. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
There is a syntax error with quotes around dig0 and dig1 signal identifiers, so try to change case "dig0" is to case dig0 is, and case "dig1" is to case dig1 is.
But anyway, the Xilinx parser is not robust enough since it crashes, so it is a good habit to create a WebCase for issues like this, so Xilinx can improve in the future.
I would follow the error message directions. Specifically:
For technical support on this issue, please open a WebCase with this
project attached at http://www.xilinx.com/support
Related
I'm a beginner to VHDL, trying to write a code that counts from 0000 to 0099 on my board (BASYS-3) depending on which switches I press. Problem is, I need one switch for shutting the program on and off, 4 switches for showing the far right decimal digit and 4 other for showing the "tens" (like the 1 in 17).
There are more switches on the board (in total 16) but I thought 4 is most logical because of the binary codings of decimals (like 9 = 1001 in binary is the largest).
I have no idea on what gates to use so the work I've done is very limited, sorry about that.
process(bcd_display)
begin
case bcd_display is
when "0000" => LED <= "0000001";
when "0001" => LED <= "1001111";
when "0010" => LED <= "0010010";
when "0011" => LED <= "0000110";
when "0100" => LED <= "1001100";
when "0101" => LED <= "0100100";
when "0110" => LED <= "0100000";
when "0111" => LED <= "0001111";
when "1000" => LED <= "0000000";
when "1001" => LED <= "0000100";
end case;
end process;
PS: https://www.youtube.com/watch?v=H7a56D4rczU
The last 30 seconds or so shows what I'm trying to do. English is not my first language so I'm putting this in case my description was hard to understand.
For future reference, you are going to want to add full code & the testbench you are using. I still wrote out what I think will work for you.
For below. You will want to assign each switch to (bcd_display_0 & bcd_display_1). For resetting the program, assign that switch to (rst) and you will need to assign a clock to (clk). Then assign each the seven segment displays to (LED_0 & LED_1). Hopefully this gets you going. I have also attached a test bench for you.
-- BCD Entity
library ieee;
use ieee.std_logic_1164.all;
entity Display_Test is
port (
clk : in std_logic;
rst : in std_logic;
bcd_display_0 : in std_logic_vector(3 downto 0);-- assign to first set of switches
bcd_display_1 : in std_logic_vector(3 downto 0);-- assign to second set of switches
LED_0 : out std_logic_vector(6 downto 0);-- assign to first 7-segment display
LED_1 : out std_logic_vector(6 downto 0) -- assign to second 7-segment display
);
end Display_Test;
architecture behav of Display_Test is
use ieee.numeric_std.all;
begin
p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
LED_0 <= (others => '0');
LED_1 <= (others => '0');
else
case to_integer(unsigned(bcd_display_0)) is
when 0 => LED_0 <= "0000001";
when 1 => LED_0 <= "1001111";
when 2 => LED_0 <= "0010010";
when 3 => LED_0 <= "0000110";
when 4 => LED_0 <= "1001100";
when 5 => LED_0 <= "0100100";
when 6 => LED_0 <= "0100000";
when 7 => LED_0 <= "0001111";
when 8 => LED_0 <= "0000000";
when 9 => LED_0 <= "0000100";
when others => LED_0 <= "0000000";
end case;
case to_integer(unsigned(bcd_display_1)) is
when 0 => LED_1 <= "0000001";
when 1 => LED_1 <= "1001111";
when 2 => LED_1 <= "0010010";
when 3 => LED_1 <= "0000110";
when 4 => LED_1 <= "1001100";
when 5 => LED_1 <= "0100100";
when 6 => LED_1 <= "0100000";
when 7 => LED_1 <= "0001111";
when 8 => LED_1 <= "0000000";
when 9 => LED_1 <= "0000100";
when others => LED_1 <= "0000000";
end case;
end if;
end if;
end process;
end behav;
--TestBench
entity tb_bcd is
end tb_bcd;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_bcd is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal bcd_display_0 : std_logic_vector(3 downto 0);
signal bcd_display_1 : std_logic_vector(3 downto 0);
signal LED_0 : std_logic_vector(6 downto 0);
signal LED_1 : std_logic_vector(6 downto 0);
begin
clk <= not clk after 50 ns;
rst <= '0' after 200 ns;
bcd_display_0 <= "0110" after 250 ns;
bcd_display_1 <= "0010" after 280 ns;
Display_Test_inst : entity work.Display_Test
port map (
clk => clk,
rst => rst,
bcd_display_0 => bcd_display_0,
bcd_display_1 => bcd_display_1,
LED_0 => LED_0,
LED_1 => LED_1
);
end behav;
I'm having a bit of problem when trying to test bench my VHDL.
I'm using a fpga Baysis 2 to run my code, and it is working pretty well on the hardware, but when I use the program Isim to simulate my code, it doesn't show any behavior for my out pins, only the letter U.
I'm looking through the internet and couldn't find a solution, can someone help me on this one?
Here follows the last part of my code (probably the one with the something wrong). Before that the code simply had a process to divide the clock to measure 1 second another to divide in 1/200 of a second to quickly turn on and off the led's on the fpga's display, and counted the seconds to make the 24 hour clock work, of course.
contador: process(clk200)
variable flag : std_logic_vector (1 downto 0);
-- ledplex is the mux that controls which display should be on
-- Segm is the 7 segments display
-- mu md hu hd are the signals with the time information
begin
if(clk200'event and clk200='1') then
if (flag = "00") then
ledplex <= "1110";
case mu is
when 0 => segm <= "1000000";
when 1 => segm <= "1111001";
when 2 => segm <= "0100100";
when 3 => segm <= "0110000";
when 4 => segm <= "0011001";
when 5 => segm <= "0010010";
when 6 => segm <= "0000011";
when 7 => segm <= "1111000";
when 8 => segm <= "0000000";
when 9 => segm <= "0011000";
when others => segm <= "1111111";
end case;
flag := "01";
elsif (flag = "01") then
ledplex <= "1101";
case md is
when 0 => segm <= "1000000";
when 1 => segm <= "1111001";
when 2 => segm <= "0100100";
when 3 => segm <= "0110000";
when 4 => segm <= "0011001";
when 5 => segm <= "0010010";
when others => segm <= "1111111";
end case;
flag := "10";
elsif (flag = "10") then
ledplex <= "1011";
case hu is
when 0 => segm <= "1000000";
when 1 => segm <= "1111001";
when 2 => segm <= "0100100";
when 3 => segm <= "0110000";
when 4 => segm <= "0011001";
when 5 => segm <= "0010010";
when 6 => segm <= "0000011";
when 7 => segm <= "1111000";
when 8 => segm <= "0000000";
when 9 => segm <= "0011000";
when others => segm <= "1111111";
end case;
flag := "11";
elsif (flag = "11") then
ledplex <= "0111";
case hd is
when 0 => segm <= "1000000";
when 1 => segm <= "1111001";
when 2 => segm <= "0100100";
when others => segm <= "1111111";
end case;
flag := "00";
end if;
end if;
end process contador;
and here follows the test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_b IS
END t_b;
ARCHITECTURE behavior OF t_b IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hora
PORT(
clk25m : IN std_logic;
segm : OUT std_logic_vector(6 downto 0);
ledplex : OUT std_logic_vector(3 downto 0);
x : out std_logic
);
END COMPONENT;
signal clk_tb : std_logic := '0';
signal segm_tb : std_logic_vector(6 downto 0);
signal ledplex_tb : std_logic_vector(3 downto 0);
signal x_tb : std_logic;
BEGIN
CUT: hora port map( clk25m => clk_tb,
segm => segm_tb,
ledplex => ledplex_tb,
x => x_tb);
Test_Vector: process
begin
clk_tb <= '1';
wait for 40 ns;
clk_tb <= '0';
wait for 40 ns;
end process;
END behavior;
You did not initialize your variable flag. Without this your variable may be undefined, hence U. Use the following:
variable flag : std_logic_vector (1 downto 0) := "00"; -- initialize variable
Hello can somebody help me with something thats been bugging me for a while. I have a simple case statement and to the best of my knowledge the syntax is good. see the below code
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY D7SEGSEL IS
PORT (
SW :in std_logic_vector(3 DOWNTO 0);
SEG :out std_logic_vector(6 DOWNTO 0)
);
END ENTITY D7SEGSEL;
ARCHITECTURE behavioral OF D7SEGSEL IS
BEGIN
CASE SW IS
WHEN "1000000" => SEG <= "0000";
"1111001" => SEG <= "0001";
"0100100" => SEG <= "0010";
"0110000" => SEG <= "0011";
"0011001" => SEG <= "0100";
"0010010" => SEG <= "0101";
"0000010" => SEG <= "0110";
"1111000" => SEG <= "0111";
"0000000" => SEG <= "1000";
"0011000" => SEG <= "1001";
"0001000" => SEG <= "1010";
"0000011" => SEG <= "1011";
"1000110" => SEG <= "1100";
"0100001" => SEG <= "1101";
"0000110" => SEG <= "1110";
"0001110" => SEG <= "1111";
END CASE;
END ARCHITECTURE behavioral;
its for a simple 7SEG LED driver, each time i compile the code though I get the following error messages:
Error (10500): VHDL syntax error at D7SEGCASE.vhd(19) near text
"CASE"; expecting "end", or "(", or an identifier ("case" is a
reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at D7SEGCASE.vhd(21) near text "=>"; expecting > "(", or
"'", or "."
Can anyone point out the obvious in what I'm doing wrong
I have already made a decoder for the 7seg with a select/when statement but want to practice the use of case and then make it synchronous with the addition of a clock input
You have a few problems.
You are missing your process statement.
You are missing subsequent "when" after your first condition.
You have reversed your condition and your assignment in your WHEN conditions.
See fixes below:
ARCHITECTURE behavioral OF D7SEGSEL IS
BEGIN
my_case : process(sw, seg)
begin
CASE SW IS
WHEN "0000" => SEG <= "1000000";
WHEN "0001" => SEG <= "1111001";
-- Other Assignments follow...
END CASE;
end process my_case;
END ARCHITECTURE behavioral;
As pointed out by others, there are some problems with your code, but luckily there are different options to implement what you want.
Case (process)
process (SW) is
begin
case SW is
when "0000" => SEG <= "1000000";
when "0001" => SEG <= "1111001";
when "0010" => SEG <= "0100100";
when "0011" => SEG <= "0110000";
when "0100" => SEG <= "0011001";
when "0101" => SEG <= "0010010";
when "0110" => SEG <= "0000010";
when "0111" => SEG <= "1111000";
when "1000" => SEG <= "0000000";
when "1001" => SEG <= "0011000";
when "1010" => SEG <= "0001000";
when "1011" => SEG <= "0000011";
when "1100" => SEG <= "1000110";
when "1101" => SEG <= "0100001";
when "1110" => SEG <= "0000110";
when "1111" => SEG <= "0001110";
when others => SEG <= (others => 'X');
end case;
end process;
When (concurrent)
SEG <= "1000000" when SW = "0000" else
"1111001" when SW = "0001" else
"0100100" when SW = "0010" else
"0110000" when SW = "0011" else
"0011001" when SW = "0100" else
"0010010" when SW = "0101" else
"0000010" when SW = "0110" else
"1111000" when SW = "0111" else
"0000000" when SW = "1000" else
"0011000" when SW = "1001" else
"0001000" when SW = "1010" else
"0000011" when SW = "1011" else
"1000110" when SW = "1100" else
"0100001" when SW = "1101" else
"0000110" when SW = "1110" else
"0001110" when SW = "1111" else
(others => 'X');
Select (concurrent)
d7seg : with SW select
SEG <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0011000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when "1111",
(others => 'X') when others;
The Select (concurrent) is compact and with few repetitions, and is likely to yield a small implementation, so will be a good choice.
I can't see process in your code.
process(sw,seg)
.
.
.
end process
check if you get after adding it
I have a 4x3 keypad, i wrote this FSM for interfacing it with my Nexys2 board, trouble I am having here is
When I run the code, the LEDs glow without any key pressed, it shows random combinations automatically
When I press a key it shows that particular combination then goes on to the next condition of ROW without any key pressed. And sometimes it does not even respond if i press a key.
What is happening? What is wrong with this code? I am clueless. Can someone point out the mistakes and suggest some solution? Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity keypad_3x4 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ROW : in STD_LOGIC_VECTOR (3 downto 0);
COL : out STD_LOGIC_VECTOR (2 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0)
);
end keypad_3x4;
architecture Behavioral of keypad_3x4 is
architecture Behavioral of keypad_3x4 is
TYPE STATE_TYPE is
( RESET_ST,
S1,
S2,
S3,
S4,
S5,
S6
);
signal state: STATE_TYPE;
begin
process (CLK, RESET)
begin
if (RESET = '1') then
state <= RESET_ST;
elsif (CLK'event and CLK = '1') then
case (state) is
WHEN RESET_ST =>
LED <= (others => '0');
COL <= (others => '0');
state <= S1;
WHEN S1 =>
COL <= "001"; --C1 selected
LED <= (others => '0');
state <= S2;
WHEN S2 =>
if ROW <= "0001" then
led <= "0001"; --1
elsif ROW <= "0010" then
led <= "0100"; --4
elsif ROW <= "0100" then
led <= "0111"; --7
elsif ROW <= "1000" then
led <= "1111"; --*
else
LED <= (others => '0');
state <= S3;
end if;
WHEN S3 =>
COL <= "010"; --C2 selected
LED <= (others => '0');
state <= S4;
WHEN S4 =>
if ROW <= "0001" then
led <= "0010"; --2
elsif ROW <= "0010" then
led <= "0101"; --5
elsif ROW <= "0100" then
led <= "1000"; --8
elsif ROW <= "1000" then
led <= "0000"; --0
else
LED <= (others => '0');
state <= S5;
end if;
WHEN S5 =>
COL <= "100"; --C3 selected
LED <= (others => '0');
state <= S6;
WHEN S6 =>
if ROW <= "0001" then
led <= "0011"; --3
elsif ROW <= "0010" then
led <= "0110"; --6
elsif ROW <= "0100" then
led <= "1001"; --9
elsif ROW <= "1000" then
led <= "1111"; --#
else
LED <= (others => '0');
state <= RESET_ST;
end if;
WHEN others =>
state <= RESET_ST;
END case;
END if;
END process;
end Behavioral;
This code selects either the leds or the 7 segment display to show it's 8-bit data that i feed in through the switches. I select the led or the 7 segment through a push button. When I try to run it on my nexys2 board the led part works fine but as i press the pushbutton the selected 7segment glows and changes its value with the led glowing as well. Also the 7 segment changes it's value only when i press the pushbuton again. I am a newbie and i think I am having trouble making a good logic or what is the issue? any help would be appreciated!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity selector is
Port ( clk: in STD_LOGIC;
sel : in STD_LOGIC;
comb : in STD_LOGIC_VECTOR (7 downto 0);
segment : out STD_LOGIC_VECTOR (3 downto 0);
number : out STD_LOGIC_VECTOR (6 downto 0);
led: out STD_LOGIC_VECTOR (7 downto 0));
end selector;
architecture Behavioral of selector is
begin
process (clk, comb, sel) begin
if (clk'event and clk = '1') then
if sel = '1' then
segment <= "1110";
case (comb) is
when "00000000" => number <= "0000001"; --0
when "00000001" => number <= "1001111"; --1
when "00000010" => number <= "0010010"; --2
when "00000011" => number <= "0000110"; --3
when "00000100" => number <= "1001100"; --4
when "00000101" => number <= "0100100"; --5
when "00000110" => number <= "0100000"; --6
when "00000111" => number <= "0001111"; --7
when "00001000" => number <= "0000000"; --8
when "00001001" => number <= "0000100"; --9
when others => number <= "1111111"; -- off
end case;
elsif sel = '0' then
case (comb) is
when "00000000" => led <= "00000000"; --0
when "00000001" => led <= "00000001"; --1
when "00000010" => led <= "00000011"; --2
when "00000011" => led <= "00000111"; --3
when "00000100" => led <= "00001111"; --4
when "00000101" => led <= "00011111"; --5
when "00000110" => led <= "00111111"; --6
when "00000111" => led <= "01111111"; --7
when "00001000" => led <= "11111111"; --8
when others => led <= "00000000"; -- off
end case;
end if;
end if;
end process;
end Behavioral;
You are not changing the value for the output that is not selected, so it remains in the state it has been assigned last.
Also, your code your code will only ever have an effect on the rising edge of the clock, so the sensitivity list can be reduced to (clk) (at which point, clk'event is implied).