VHDL Method Call - vhdl

Question

Is it possible to write a code segment and call it, instead of writing that segment many times? Ie. I want to reuse a segment of code as shown below:
process (currentState)
begin
case currentState is
when requiredCoinsTensAnode => anodes <= "100000";--turn on the tens display
case tensCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
nextState <= requiredCoinsUnitsAnode;--just displayed the tens digit, next we need to display the units digit
when requiredCoinsUnitsAnode => anodes <= "010000";--turn on the units display
case unitsCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
nextState <= insertedCoinsTensAnode;
end case;
end process;

Answer 1

Functions are one option, as ravi has pointed out.
function f_segDisplay (
signal segCount : std_logic_vector(6 downto 0))
return std_logic_vector(3 downto 0) is
begin -- f_segDisplay
case segCount is
when "0000" => return "1111110"; --0
when "0001" => return "0110000"; --1
when "0010" => return "1101101"; --2
when "0011" => return "1111001"; --3
when "0100" => return "0110011"; --4
when "0101" => return "1011011"; --5
when "0110" => return "1011111"; --6
when "0111" => return "1110000"; --7
when "1000" => return "1111111"; --8
when others => return "1111011"; --9
end case;
end f_segDisplay;
process (currentState, tensCount, unitsCount)
begin
case currentState is
when requiredCoinsTensAnode =>
anodes <= "100000"; --turn on the tens display
segDisplay <= f_segDisplay(tensCount);
nextState <= requiredCoinsUnitsAnode;
when requiredCoinsUnitsAnode =>
anodes <= "010000"; --turn on the units display
segDisplay <= f_segDisplay(unitsCount);
nextState <= insertedCoinsTensAnode;
end case;
end process;
Depending on the compiler and options, it may decide to put the function code in-line. This would cause multiple instances of the logic to be placed, much like your original code.
An alternative is that you take the common code out into another process:
p_segdisplay : process (segCount)
begin -- process p_segdisplay
case segCount is
when "0000" => segDisplay <= "1111110"; --0
when "0001" => segDisplay <= "0110000"; --1
when "0010" => segDisplay <= "1101101"; --2
when "0011" => segDisplay <= "1111001"; --3
when "0100" => segDisplay <= "0110011"; --4
when "0101" => segDisplay <= "1011011"; --5
when "0110" => segDisplay <= "1011111"; --6
when "0111" => segDisplay <= "1110000"; --7
when "1000" => segDisplay <= "1111111"; --8
when others => segDisplay <= "1111011"; --9
end case;
end process p_segdisplay;
process (currentState, tensCount, unitsCount)
begin
case currentState is
when requiredCoinsTensAnode =>
anodes <= "100000"; --turn on the tens display
segCount <= tensCount;
nextState <= requiredCoinsUnitsAnode;
when requiredCoinsUnitsAnode =>
anodes <= "010000"; --turn on the units display
segCount <= unitsCount;
nextState <= insertedCoinsTensAnode;
end case;
end process;
BTW: You need tensCount and unitsCount in your sensitivity list.
Abstracting a common resource like this is a useful technique when doing area or power concious designs.
Both should work in the same way, and perfect tools would produce the same logic from the two, but we rarely have perfect tools. Experiment with different styles. Some produce better results on some tools, some on others.

Answer 2

Yes, you can use functions in VHDL.
check http://www.csee.umbc.edu/portal/help/VHDL/design.html#funcd
http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_3.htm

Answer 3

That code is probably best in a function or procedure.
An entity is another way to encapsulate code in VHDL.