In the method of paging in the operating system memory management issues.
when we have 64 byte for Pages ,why 6 bit needed?
111111 ==> 63
1000000 => 64
Using 6 bits you can represent maximum 64 pages(0-63) in binary. As one single bit can take only two values 0 or 1,so for 6 bits you have 2*2*2*2*2*2 or 26 different permutations.Every permutation will identify a different page.
Related
So Im having trouble understanding some parts to direct mapped caching. I have a byte addressed memory system that has 64KB memory with a 2KB direct-mapped cache. Cache blocks are 32 bytes.
From what I understand and please correct me if i'm wrong, I have 2048B/32B = 64 cache blocks. I need to figure out how many total bits are needed for each cache entry (tag, "dirty" bit, etc).
I believe i'll need 6 index bits (2^6 = 64 (# of blocks))
and 5 offset bits (2^5 = 32 (size of cache block))
Im just having trouble figuring out the rest that are needed.
The bits of a physical address can be split into 3 groups - the least significant group of bits that determine "offset of byte within cache block" and doesn't need to be stored in the tag, the middle group of bits that determine "index of cache block within the cache" and doesn't need to be stored in the tag, and the most significant group of bits that is used to check if the data in the cache is the data you want which must be stored in the tag.
With 64 KiB of physical address space a physical address would have 16 bits; and if your cache is 2048 bytes then (for "direct mapped") the least significant group of bits and the middle group of bits combined must add up to a total of 11 bits. That means the most significant group of bits (which must be stored in the tag) needs to be 5 bits (because 16 bits - 11 bits = 5 bits).
For other bits; you always need something to indicate if the entry is used or empty; if the cache is "write-back" you need a dirty bit but if the cache is "write-through" you don't; if there are multiple CPUs and cache coherency you need more bits for that (e.g. exclusive/shared); and if there's any kind of error detection or correction you need more bits for that (e.g. a "parity bit"). This means the total tag size is at least 6 bits (but may be more).
Just to make sure, does every single address contain one byte? So say you had theoretical addresses FFF0 and FFFF: there are 16 values between these two addresses, which means between them they contain 16 bytes, or 8 x 16 bits? Every individual address is linked to a single byte?
Just to make sure, does every single address contain one byte?
...which means between them they contain 16 bytes, or 8 x 16 bits?
Every individual address is linked to a single byte?
Yes to all three questions.
Which is why the limitation with 32-bit addressing, you can only access 2^32 bytes == 4,294,967,296 bytes == 4 GiB. Each addressable memory location gives access to 1 byte.
If we could access 2 bytes with one address, then that limit would have been 8 GiB. And the architecture of modern chips and all software would have to be modified to determine whether they want both bytes or just the first or the second. So you'd need, say, 1 more bit to determine that. Guess what, if you had 33-bit machines, that's what we'd get...max address-able space of 8 GiB. Which is still effectively 1-byte-containing addresses. Workarounds do exist but that's not related to your questions.
* GiB = Binary GigaBytes.
Note that this is not related to "types" where a char is 1 byte and an int is 4 bytes. Programming languages compensate for that when trying to access the value of a stored variable/data stored at a location(s). And they are actually calculated as total bits rather than total bytes. So an int is considered as 32 bits rather than 4 bytes. When C fetches an int's value from memory, it will fetch all 4 bytes even though the address of the int refers to just one, the address of the first byte.
Yes. Addresses map to bytes 1 to 1, even if they expect you to work with a word size of two or four bytes at a time.
if a computer system with memory module of size 2048 and each word is 8 bits, it has four fields:
an op-code field to specify one of 32 operations,
a register address to select one of 64 registers,
an address mode enabling one of 4 modes and a memory address field.
draw the instruction indicating its fields.
Let's try:
ooooorrr rrrmmddd dddddddd
A.: three words.
We have 32 operations, 32 is a 2^5, so we need 5 bits to encode the operation.
Then we have 64 registers, it is 2^6, so we need 6 bits to encode the register.
Then we have 4 addressing modes, so 2 more bits. And, finally we have 2048 addresses and we need 11 bits to encode the displacement.
So, totally we need 24 bits (5+6+2+11) to encode the single instruction. Thus, provided that this machine word is 8 bits wide we need 3 words to encode an instruction.
I have a very simple (n00b) question.
A 20-bit external address bus gave a 1 MB physical address space (2^20
= 1,048,576).(Wikipedia)
Why 1 MByte?
2^20 = 1,048,576 bit = 1Mbit = 128KByte not 1MB
I misunderstood something.
When you have 20 bits you can address up to 2^20. This is your range, not the number of bits.
I.e. if you have 8 bits your range is up to 255 (unsigned) not 2^8 bits.
So with 20 bits you can address up to 2^20 bytes i.e. 1MB
I.e. with 20 bits you can represent addresses from 0 up to 2^20 = 1,048,576. I.e. you can reference up to 1MB of memory.
1 << 20 addresses, that is 1,048,576 bytes addressable. Hence, 1 MB physical address space.
Because the smallest addressable unit of memory (in general - some architectures have small bit-addressable pieces of memory) is the byte, not the bit. That is, each address refers to a byte, rather than to a bit.
Why, you ask? Direct access to individual bits is almost never needed - and if you need it, you can still load the surrounding byte and get the bit with bit masks and shifts. Increasing the bits per address allows you to address more memory with the same address range.
Note that a byte doesn't have to be 8 bit, strictly speaking, though it's ubiquitous by now. But regardless of the byte size, you're grouping bits together to be able to handle larger quantities of them.
I'm taking a programming fundamentals course and currently I'm on the chapter where it talks about computer organization and operations on bits - how the CPU (ALU, CU, registers, etc.) works.
I have a fairly good understanding of the binary language. I understand sign/magnitude format/ 1's complement, 2's complement, etc.
In the book I've learned that a nibble = 4 bits, 8 bits = 1 byte next is a word - which is usually in groups: 8 bits, 16 bits, 32 bits or 64 bits (so on), and all this makes perfect sense to me. Here's my homework question which is kind of confusing to me:
"A computer has 64 MB of memory, Each word is 4 bytes. How many bits are needed to address each single word in memory?"
Well, I'm confused now. The book just told me that a word is typically in multiples of 8.
However I know that 1 byte = 8 bits, so since there are 4 bytes and 1 byte = 8 bytes, would it be correct to think that 4 bytes x 8 bits = 32 bits? Is this the answer?
A 1-bit address can address two words (0, 1).
A 2-bit address can address four words (00, 01, 10, 11).
A 3-bit address can address eight words (000, 001, 010, 011, 100, 101, 110, 111).
So first answer: How many words do you have? Then answer: How many bits does your address need in order to address them?
64MB = 67108864 Bytes/4 Bytes = 16777216 words in memory, and each single word can thus be addressed in 24 bits (first word has address 000000000000000000000000 and last has address 111111111111111111111111). Also 2 raised to 24 = 16777216, so 24 bits are needed to address each word in memory.
The requirement is to represent each memory word with an address, which is in bits, in such a way that each and every word can be represented.
For example, to represent 4 words, you need 4 addresses, 2 raised to 2 is 4, so you need two bits. 00 is the address of the first word, 01 is the address of the second word, 10 is the address of the third word, and 11 is the address of the 4th word.
For 8 words, you need 8 addresses, and 2 raised to 3 is 8, so 3 bits are needed. 000, 001, 010, 011, 100, 101, 110, 111 are the 8 addresses.
1 byte = 8 bits, so since there are 4 bytes and 1 byte = 8 bites Would it be correct to think 4bytes x 8 bites = 32 bits?? being the answer???
No, that's not the answer. If your computer has 64 MB of memory and each word is 4 bytes, how many words are there in your memory? How much bits would you need to address each word (bits needed to represent a number from 0 to number of words - 1).
The formula being:
log (Memory Size/Addressable Unit Size) / log 2
Example1:
How many address bits are required to address 16GBytes of memory, where each addressable unit is 1 byte wide?
Ans: log(16*1024*1024*1024/1)/log2 = 34 bits
Example2:
How many address bits are required to address 16GBytes of memory, where each addressable unit is 2 bytes wide?
Ans: log(16*1024*1024*1024/2)/log2 = 33 bits
Example3:
How many address bits are required to address 64MBytes of memory, where each addressable unit is 4 bytes wide?
Ans: log(64*1024*1024/4)/log2 = 24 bits
Example3:
How many address bits are required to address 16MBytes of memory, where each addressable unit is 1 byte wide?
Ans: log(16*1024*1024/1)/log2 = 24 bits