if a computer system with memory module of size 2048 and each word is 8 bits, it has four fields:
an op-code field to specify one of 32 operations,
a register address to select one of 64 registers,
an address mode enabling one of 4 modes and a memory address field.
draw the instruction indicating its fields.
Let's try:
ooooorrr rrrmmddd dddddddd
A.: three words.
We have 32 operations, 32 is a 2^5, so we need 5 bits to encode the operation.
Then we have 64 registers, it is 2^6, so we need 6 bits to encode the register.
Then we have 4 addressing modes, so 2 more bits. And, finally we have 2048 addresses and we need 11 bits to encode the displacement.
So, totally we need 24 bits (5+6+2+11) to encode the single instruction. Thus, provided that this machine word is 8 bits wide we need 3 words to encode an instruction.
Related
Encountered this problem and the solution said
"32 bit address bits, 64 byte line means we have 6 bits for the word address in the line that aren't in the tag, 32,768 bytes in the cache at 64 byte lines is 512 total lines, which means we have 12 bits of address for the cache index, write back means we need a dirty bit, and we always need a valid bit. So each line has 64*8=512 data bits, 32-6- 12=14 tag bits, and 2 flag bits: data/total bits = 512/(512+14+2)=512/528."
When I tried to solve the problem I got 32kB/64byte=512 lines in total, i.e. 2^9=512. In addition, a 64 byte cache line size, 1 word=4 bytes, is 64/4=16 words per line i.e. 2^4.
To my understanding the total amount of bits in a cache is given by total amount of entries/lines in the caches*(tag address + data)-> 2^9*((32-9-4+2)+16*32). Thus, the amount of data bits per cache line is 512 (16 words *32 bits per word), and the tag is 32-9-4+2=21 (the 9 is the cache index for direct mapped cache, the 4 is to address each word and the 2 is the valid bit and dirty bit)
Effectively, the answer should be 512/533 and not 512/528.
Correct?
512 lines = 9 bits not 12 as they claim, so you are right on this point.
However, they are right that 64 byte lines gives 6 bits for the block offset — though it is a byte offset, not word as they say.
So, 32-6-9=17 tag bits, then plus the 2 for dirty & valid.
FYI, there's nothing in the above problem that indicates a conversion from bytes to words. While it is true that there will be 16 x 32-bit words per line (i.e. 64 bytes per line) it is irrelevant: we should presume that the 32-bit address is a byte address unless otherwise stated. (It would be unusual to state cache size in bytes for a word (not byte) addressable machine; it would also be unusual for a 32-bit machine to be word addressable — some teaching architectures like LC-3 are word addressable, however, they are 16-bits; other word addressable machines have odd sizes like 12 or 18 or 36 bit words — though those pre-date caches!)
So Im having trouble understanding some parts to direct mapped caching. I have a byte addressed memory system that has 64KB memory with a 2KB direct-mapped cache. Cache blocks are 32 bytes.
From what I understand and please correct me if i'm wrong, I have 2048B/32B = 64 cache blocks. I need to figure out how many total bits are needed for each cache entry (tag, "dirty" bit, etc).
I believe i'll need 6 index bits (2^6 = 64 (# of blocks))
and 5 offset bits (2^5 = 32 (size of cache block))
Im just having trouble figuring out the rest that are needed.
The bits of a physical address can be split into 3 groups - the least significant group of bits that determine "offset of byte within cache block" and doesn't need to be stored in the tag, the middle group of bits that determine "index of cache block within the cache" and doesn't need to be stored in the tag, and the most significant group of bits that is used to check if the data in the cache is the data you want which must be stored in the tag.
With 64 KiB of physical address space a physical address would have 16 bits; and if your cache is 2048 bytes then (for "direct mapped") the least significant group of bits and the middle group of bits combined must add up to a total of 11 bits. That means the most significant group of bits (which must be stored in the tag) needs to be 5 bits (because 16 bits - 11 bits = 5 bits).
For other bits; you always need something to indicate if the entry is used or empty; if the cache is "write-back" you need a dirty bit but if the cache is "write-through" you don't; if there are multiple CPUs and cache coherency you need more bits for that (e.g. exclusive/shared); and if there's any kind of error detection or correction you need more bits for that (e.g. a "parity bit"). This means the total tag size is at least 6 bits (but may be more).
Just to make sure, does every single address contain one byte? So say you had theoretical addresses FFF0 and FFFF: there are 16 values between these two addresses, which means between them they contain 16 bytes, or 8 x 16 bits? Every individual address is linked to a single byte?
Just to make sure, does every single address contain one byte?
...which means between them they contain 16 bytes, or 8 x 16 bits?
Every individual address is linked to a single byte?
Yes to all three questions.
Which is why the limitation with 32-bit addressing, you can only access 2^32 bytes == 4,294,967,296 bytes == 4 GiB. Each addressable memory location gives access to 1 byte.
If we could access 2 bytes with one address, then that limit would have been 8 GiB. And the architecture of modern chips and all software would have to be modified to determine whether they want both bytes or just the first or the second. So you'd need, say, 1 more bit to determine that. Guess what, if you had 33-bit machines, that's what we'd get...max address-able space of 8 GiB. Which is still effectively 1-byte-containing addresses. Workarounds do exist but that's not related to your questions.
* GiB = Binary GigaBytes.
Note that this is not related to "types" where a char is 1 byte and an int is 4 bytes. Programming languages compensate for that when trying to access the value of a stored variable/data stored at a location(s). And they are actually calculated as total bits rather than total bytes. So an int is considered as 32 bits rather than 4 bytes. When C fetches an int's value from memory, it will fetch all 4 bytes even though the address of the int refers to just one, the address of the first byte.
Yes. Addresses map to bytes 1 to 1, even if they expect you to work with a word size of two or four bytes at a time.
A memory module has a data bus that is 128 bits wide. If module holds 4GB (2^31 bytes), how many address bits are redundant?
I believe there is some sort of formula (if not a formula a logical procedure) which we can use to find out the address bus then from there we can find out the redundant number of address bits. I don't have a basic idea of how these things are related: address bus, bus width, data bus.etc.
Each line on one of those parallel buses represents one bit of information. This is why the number of lines that comprise the bus is also referred to its width in bits.
The address bus is used to send the address to be read from or written to to the memory module. Because each line can 'transport' only one bit multiple lines are used in parallel.
For example, to be able to address 256 different locations in the memory, (at least) 8 lines are required for the address bus (because 2^8 = 256). Those 4 billion memory locations will therefor need 32 bus lines on the address bus, the address bus is 32 bits wide.
Note that I used the word "memory location" above, because the address sent to the memory module may refer to bytes or to some other unit of storage, like "words" (2 bytes) or "double-words" (4 bytes) or something else.
How big the minumum unit of storage that can be directly addressed is depends on the memory module and its internal organisation.
A memory module with a bus width of 128 bits for the data bus can send or receive 128 bits = 16 bytes at the same time. For this kind of memory the smallest addressable unit may be 128 bits, so that it could be accessed only in blocks of 16 bytes, which are usually aligned on multiples of this block size.
In that case, the first block of 16 bytes would be addressed by address 0 and would occupy the first 16 bytes of memory. Then at address 1 would be the next block, starting at byte #16. Address 2 gives 16 bytes from byte #32, and so on.
So, if each address on the address bus is used to address 16 bytes at the same time, less addresses will be needed to access the whole memory as compared to byte-wise addressing.
To be able to address each byte of those 4GB individually, the address bus needs to be 32 bits wide (2^32 bytes= 4GB). If, however, only whole blocks of 16 bytes can be addresses individually, one will only need (2^32)/16 different addressed to address the whole memory. 16 = 2^4, so (2^32)/(2^4) = 2^28. -> 28 bits would be needed to address each whole block of 16 bytes (=128 bits) and the width of the address bus could potentially be reduced to 28 lines.
Let’s say we have a 32-bit address, so each bit can be either 1 or 0.
So the total number of combinations is equal to 2^32.
So we can represent 2^32 addresses (without unit).
But why do people say a 32-bit address can represent 2^32 byte addresses (why “byte” addresses)?
I already read Why does a 32-bit OS support 4 GB of RAM?
Won’t it become 2^32 * 8 bits addresses? Why can people simply add “byte” at the end?
Because memory is byte-addressable rather than bit-addressable.
The address 0x100 refers to a single byte and the address 0x101 refers the following byte.
Each address points to a byte. In memory, it is not the single bits that are addressed but instead bytes.
So, 32bits will give you an addressable space of 2^32 items, each item being a full byte. Yes, it could have been made so that each address points to a specific bit, but no, they made each address point to a byte.