VHDL multiplexer testbench error - vhdl

I am new to vhdl and trying to make testbench for multiplexer with 5 select lines but it gives me errors (the code is very long so I just copied the part which include the errors )
The code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Mux_4_to_1_tb is
end Mux_4_to_1_tb;
architecture tb of Mux_4_to_1_tb is
component Mux_4_to_1 is
port( clock : in std_logic;
D0, D1, D2, D3 : in std_logic; -- the data lines D0=A0 D1=A1 D2=B0 D3=B1
S0, S1, S2, S3, S4 : in std_logic; -- the selector switches
F : out std_logic_vector(2 downto 0)
);-- the output
end component;
constant clockperiod : time := 20 ns;
signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 , F : std_logic;
signal selectors : std_logic_vector(4 downto 0);
begin
mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
--Concurrent processes
process
begin
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
S0 <= '1'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
end process;
process(S4, S3, S2, S1, S0)
begin
selectors <= S0&S1&S2&S3&S4;
end process;
process
begin
--The "assert" keyword allows you to test certain
--conditions. In other words, the point of assertion is
--to allow you to inspect what you expect.
--Two test cases are presented here. Feel free
--to add your own cases.
--TEST 1
D0 <= '0';
D1 <= '1';
D2 <= '0';
D3 <= '1';
wait for clockperiod;
case selectors is
when "00000" =>
assert(F => "000") report "Error 1: 00000" severity error;
Error:
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): (vcom-1581) No feasible entries for infix operator '='.** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
The error point me to the line with the assert word.
Also i get this error at the end of the code
code:
when others =>
assert true;
end case;
end process;
end tb;
Error:
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(229): VHDL Compiler exiting
The error point me to the last line here.

You're not providing any insight into how this testbench is supposed to operate without revealing the contents of Mux_4_to_1.
There are two things wrong with the assertion statement condition:
assert(F => "000")
F is declared as type std_logic which is not an array type and can't be compared to a string value (which would have an array type determinable by context). Also the relational operator should be >= and not =>, read as 'greater than or equal to'. => is a delimiter used in association.
Changing the relational operator and changing the declaration for F:
signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 : std_logic; -- , F : std_logic;
signal F: std_logic_vector (2 downto 0);
generate an error telling us F can't be associated with S4, telling us you have a parameter list error. You don't have enough parameters. It's not an error to not provide an association for outputs which is why it wasn't noticed before, although the reader might assume you changed the declaration of F to get rid of that error a priori.
Adding a signal declaration for a clock:
constant clockperiod : time := 20 ns;
signal clock: std_logic;
and adding an association:
begin
-- mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
mapping:
Mux_4_to_1
port map (
clock => clock,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
S0 => S0,
S1 => S1,
S2 => S2,
S3 => S3,
S4 => S4,
F => F
);
allows your code to analyze(by concatenating the code found with the others choice to the end of the VHDL code, you don't provide a Minimal, Complete and Verifiable example).
NOTES:
clock is not shown driven in the change description and if needed for your tests should be driven by the testbench.
Formal association is shown in the port map for the instantation of Mux_4_to_1, it allows you to see missing or wrong formal to actual port associations.
Superfluous parentheses surrounding conditions may obscure errors. They are only legal if the expression they contain is legal without them. It can change the error message you see. The lack of a proper relational operator results in a syntax error.

Related

VHDL Error simulating a Mealy Finite State Machine sequence detector

I'm writing code for a Mealy FSM sequence detector with detection of input sequences 01110010 and 00100111. Overlapping is allowed.
I can compile both the code and had set the top level to the testbench but when I simulate I'm not getting any waveform.
This is the circuit code
library ieee;
use ieee.std_logic_1164.ALL;
entity SequenceDetector_8bit is
port( X : in std_logic;
RST: in std_logic;
CLK: in std_logic;
Z : out std_logic);
end SequenceDetector_8bit;
architecture Behavior of SequenceDetector_8bit is
type state is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13);
signal PresentState, NextState : state;
signal Z0: std_logic;
begin
clk_process:process(CLK,RST)
begin
if RST = '1' then
PresentState <= S0;
elsif rising_edge(CLK) then
PresentState <= NextState;
end if;
end process clk_process;
state_process: process(PresentState, X) -- process executed if state variables.
begin
case PresentState is -- check present state,
when S0 => -- when present state is state-S0
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S1; -- and advance to state-S1
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and stay back at state-S0
end if;
when S1 => -- when present state is state-S1
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S2; -- and advance to state-S2
end if;
when S2 => -- when present state is state-S2
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S3 => -- when present state is state-S3
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S4; -- and advance to state-S4
end if;
when S4 => -- when present state is state-S0
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S5; -- and advance to state-S5
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S0; -- and advance to state-S0
end if;
when S5 => -- when present state is state-S5
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S6; -- and advance to state-S6
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S2; -- and advance to state-S2
end if;
when S6 => -- when present state is state-S6
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S7; -- and advance to state-S7
end if;
when S7 => -- when present state is state-S7
if (X='0') then -- and when input X = 0,
Z0 <= '1'; -- produce output 1
NextState <= S10; -- and advance to state-S10
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S8 => -- when present state is state-S8
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and stay back at state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 1
NextState <= S9; -- and advance to state-S9
end if;
when S9 => -- when present state is state-S9
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S10; -- and advance to state-S10
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S3; -- and advance to state-S3
end if;
when S10 => -- when present state is state-S10
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S11; -- and advance to state-S11
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S12; -- and advance to state-S12
end if;
when S11 => -- when present state is state-S11
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S12; -- and advance to state-S12
end if;
when S12 => -- when present state is state-S12
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S8; -- and advance to state-S8
else -- when input X = 1,
Z0 <= '0'; -- produce output 0
NextState <= S13; -- and advance to state-S13
end if;
when S13 => -- when present state is state-S13
if (X='0') then -- and when input X = 0,
Z0 <= '0'; -- produce output 0
NextState <= S1; -- and advance to state-S1
else -- when input X = 1,
Z0 <= '1'; -- produce output 1
NextState <= S4; -- and advance to state-S4
end if;
end case;
end process state_process;
output_latch: process(CLK)
begin
if rising_edge(CLK) then
Z <= Z0;
end if;
end process output_latch;
end Behavior;
And this is the Test Bench code I had written
library ieee;
use ieee.std_logic_1164.ALL;
entity SequenceDetector_8bit_tb is
end SequenceDetector_8bit_tb;
architecture Behavior of SequenceDetector_8bit_tb is
--Input Signal Declaration and initialization
signal CLK : std_logic := '0';
signal X : std_logic := '0';
signal RST : std_logic := '0';
--Output Signal Declaration and initialization
signal Z : std_logic;
constant clk_period: time :=2 ms;
begin
-- instantiate the Unit Under Test (UUT)
mut: entity work.SequenceDetector_8bit
-- using position association
port map(CLK => CLK,
X => X,
RST => RST,
Z => Z);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process clk_process;
stimulus_process: process
begin
-- test sequence
X <= '0';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '0';
wait for clk_period;
X <= '0';
wait for clk_period;
X <= '1';
wait for clk_period;
X <= '0';
wait for clk_period;
wait;
end process stimulus_process;
end Behavior;

Modelsim VHDL testbench

This is my VHDL code in Modelsim. The problem is that output is uninitialized, as you can see in the image. Please tell me what's the problem with my code.
library ieee;
use ieee.std_logic_1164.All;
use IEEE.NUMERIC_STD.ALL;
entity circu_it is
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end circu_it;
architecture Behavioral of circu_it
is
Signal E ,F ,M ,N , L: std_logic;
begin
M <= (A and B and C) after 5ns;
E <= (M or D) after 5ns;
N <= (B nor C) after 5ns;
F <= (N nand A) after 5ns;
L <= not F after 2ns;
Z <= L xor E after 5ns;
end Behavioral;
The testbench of code is the following ......
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity delay_test is
end delay_test;
architecture stimulus of delay_test is
component delay
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic);
end component;
signal A: std_logic ;
signal B: std_logic ;
signal C: std_logic ;
signal D: std_logic ;
signal Z: std_logic ;
begin
DUT: delay port map ( A => A, B => B, C => C, D => D, Z => Z);
STIMULUS1: process
constant PERIOD: time := 100 ns;
begin
A <= '0';
B <= '0';
C <= '0';
D <= '0';
wait for period;
A <= '0';
B <= '0';
C <= '0';
D <= '1';
wait for period;
A <= '0';
B <= '0';
C <= '1';
D <= '0';
wait for period;
A <= '0';
B <= '0';
C <= '1';
D <= '1';
wait for period;
A <= '0';
B <= '1';
C <= '0';
D <= '0';
wait for period;
A <= '0';
B <= '1';
C <= '0';
D <= '1';
wait for period;
A <= '0';
B <= '1';
C <= '1';
D <= '0';
wait for period;
A <= '0';
B <= '1';
C <= '1';
D <= '1';
wait for period;
A <= '1';
B <= '0';
C <= '0';
D <= '0';
wait for period;
A <= '1';
B <= '0';
C <= '0';
D <= '1';
wait for period;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
wait for period;
A <= '1';
B <= '0';
C <= '1';
D <= '1';
wait for period;
A <= '1';
B <= '1';
C <= '0';
D <= '0';
wait for period;
A <= '1';
B <= '1';
C <= '0';
D <= '1';
wait for period;
A <= '1';
B <= '1';
C <= '1';
D <= '0';
wait for period;
A <= '1';
B <= '1';
C <= '1';
D <= '1';
wait;
end process;
end stimulus;
Your design entity is circu_it. You have instantiated a component called delay. You either need to
write a configuration to bind the two together
change the name of either the component or the entity so that they are the same (so that default binding occurs).

FSM Mealy Machine Sequence Detector. How to use multiple flip flops?

Right now I am working on a small project in Vivado, a Mealy FSM. The program must detect a 6 bits sequence 001011, and output "1" when the sequence is detected.
The code concerning the sequence detection is doing just fine, but besides that, it must also use Three Flip Flops: JK, D, and T.
Any advice or suggestions on how to add them?
Thank you for your time.
This is the FSM code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence is
port(
clk : in std_logic;
reset : in std_logic;
x: in std_logic;
z : out std_logic;
a : out std_logic;
b : out std_logic;
c : out std_logic;
d : out std_logic;
e : out std_logic;
f : out std_logic);
end sequence;
architecture behavioral of sequence is
type state_type is (Q0, Q1, Q2, Q3, Q4, Q5);
signal state, next_state : state_type;
begin
state_register: process (clk, reset)
begin
if (reset = '1') then --if reset is high, goto state Q0
state <= Q0;
elsif (clk'event and clk = '1') then --if not, and rising
state <= next_state; --edge, go to next state
end if;
end process;
next_state_func: process (x, state)
begin
case state is
when Q0 =>
if x = '0' then
next_state <= Q1;
else
next_state <= Q0;
end if;
when Q1 =>
if x = '0' then
next_state <= Q2;
else
next_state <= Q0;
end if;
when Q2 =>
if x = '1' then
next_state <= Q3;
else
next_state <= Q2;
end if;
when Q3 =>
if x ='0' then
next_state <= Q4;
else
next_state <= Q0;
end if;
when Q4 =>
if x = '1' then
next_state <= Q5;
else
next_state <= Q2;
end if;
when Q5 =>
if x = '1' then
next_state <= Q0;
else
next_state <= Q1;
end if;
end case;
end process;
-- This process controls the output of the sequence detector.
-- Each state has it's own output along with 'z' which indicates
-- the entire sequence 001011 has been detected.
output_func: process (x, state)
begin
case state is
when Q0 => z <= '0';
a <= '1';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q1 => z <= '0';
a <= '0';
b <= '1';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q2 => z <= '0';
a <= '0';
b <= '0';
c <= '1';
d <= '0';
e <= '0';
f <= '0';
when Q3 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '1';
e <= '0';
f <= '0';
when Q4 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '1';
f <= '0';
when Q5 => z <= '1';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '1';
end case;
end process;
end behavioral;
[1]: https://i.stack.imgur.com/pVwxL.jpg - and here is the table that contains the State Diagram Table of the FSM.
Your code is wrong. Take a look at the output_func process; this is combinatorial, and just decodes the current state, without looking at x. The a to f outputs aren't necessary, and are just a 6-bit decode of the current state - why? The z output is set when the current state is Q5, which isn't what you want - the whole process is redundant. You need to set z in your main FSM, when the current state is Q5, and x is 1 - ie. on the next_state <= Q0 transition.
On your actual question - you can't force selection of any particular F/F type with this code - the synthesiser will do whatever it wants, which means that it will implement the whole thing in D types, since JKs have been obsolete for the last 20 years. The same is probably true of T types. You need to start again, and pretend that you have a technology and a library with T, D, and JK. Write these yourself as separate entities, and re-write your code to instantiate these components, instead of allowing the synthesiser to infer them. Re-write your FSM to use JKs - the diagram you gave shows you how. In other words, derive the J and K inputs to each F/F. The z output can be a D-type. You should be able to fit in a T somewhere - I've left that as an exercise for you.

VHDL process get activated when the sensitivity list isn't changing

Process 2 keeps getting activated when there isn't a change. I have a board to test my code, and the state will change when I flip the clock(I set the clock as a button). In my code, the state will only change if I flip Qin. So it isn't doing what I wish it to do, and I spent a lot of time trying to find out what's causing it, but I can't. Please help.
This is the testbench graph TESTBENCH GRAPH
As you can see, in the graph, the output of the PS(present_state) is correct, but in the board, it isn't output right. There is one thing I found that is really important, I tried to output next_state on board, when I flip Qin to '1', the state shows "001", and then I flip clk to '1', the state become "010", which is not suppose to happen. I hope this is an important information.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VendingMechine is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Cr : in STD_LOGIC;
Qin : in STD_LOGIC;
S : in STD_LOGIC;
CB : in STD_LOGIC;
W : in STD_LOGIC;
CRo : out STD_LOGIC_VECTOR(1 DOWNTO 0);
Qo : out STD_LOGIC;
PS : out STD_LOGIC_VECTOR(2 DOWNTO 0);
Wo : out STD_LOGIC;
CBo : out STD_LOGIC;
So : out STD_LOGIC);
end VendingMechine;
architecture Behavioral of VendingMechine is
TYPE state IS(Idle, S1, S2, S3, Soda, Candy, Water);
Signal Next_State : state;
Signal Present_State : state := Idle;
begin
Process1:Process(clk, reset)
begin
if(reset = '1') THEN
Present_State <= Idle;
elsif rising_edge(clk) THEN Present_State <= Next_State;
end if;
end process;
Process2:Process(Qin, Present_State, Cr, S, w)
begin
Next_State <= Present_State;
CRo <= "00"; Qo <= '0'; PS <= "000"; Wo <= '0'; CBo <= '0'; So <= '0';
CASE Present_State IS
When Idle =>
PS <= "000";
if Qin='1' Then Next_State <= S1;
else Next_State <= Idle;
end if;
When S1 =>
PS <= "001";
if Qin='1' Then Next_State <= S2;
elsif Cr = '1' Then Cro <= "01"; Next_State <= Idle;
else Next_State <= S1;
end if;
When S2 =>
PS <= "010";
if Qin='1' Then Next_State <= S3;
elsif Cr = '1' Then CRo <="10"; Next_State <= Idle;
elsif S = '1' Then Next_State <= Soda;
elsif CB = '1' Then Next_State <= Candy;
else Next_State <= S2;
end if;
When S3 =>
PS <= "011";
if Cr = '1' Then CRo <= "11"; Next_State <= Idle;
elsif S = '1' Then Qo <= '1'; Next_State <= Soda;
elsif CB = '1' Then Qo <= '1'; Next_State <= Candy;
elsif W = '1' Then Next_State <= Water;
elsif Qin = '1' Then Qo <= '1';
else Next_State <= S3;
end if;
When Soda =>
PS <= "100";
So <= '1';
Next_State <= Idle;
When Candy =>
PS <= "101";
CBo <= '1';
Next_State <= Idle;
When Water =>
PS <= "110";
Wo <= '1';
Next_State <= Idle;
END CASE;
end process;
end Behavioral;
Process will launch not only when signals changes, but every time you assign something to signal, even if it has same value as before. That may be the reason. In parallel process you can't rely on times launch, but on result in case of some conditions, that came in inputs.
Is Qin connected to an external switch? If yes, you should implement clock-domain synchronization (and possible debouncing) on the inputs.
Please let me know in the comments if you don't know how.
Lack of clock-synchronous signals will cause glitches and thus hang-ups in the state-machine. Lack of debouncing will cause multiple switch pulses ("bouncing")

VHDL button debouncing in state machine application

I'm programming an FPGA board w/ Lattice XP2-5E chip. On board are also 4 rows and 2 columns of LED lights which I'm trying to control with 4 directional push-buttons and one reset push-button. For instance, if (1st row/1st column) LED is turned on and if I press button right, (1st row/2nd column) LED would turn on and (1st row/1st column) LED would turn off.
Since there is no built-in hardware debouncing circuit implemented, I need to implement a VHDL solution. Tick rate is 25 MHz and minimal button hold time is 25 ms. Code is shown below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SKLOP is
port ( btn_center : in std_logic;
btn_left : in std_logic;
btn_right : in std_logic;
btn_up : in std_logic;
btn_down : in std_logic;
clk_25m : in std_logic;
led : out std_logic_vector (7 downto 0));
end SKLOP;
architecture behv of SKLOP is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7);
signal CurS : state_type := s0;
signal NxtS : state_type := s0;
signal counter : std_logic_vector (22 downto 0) := (others => '0');
signal is_ok : std_logic := '0';
signal btn_press : std_logic := '0';
signal start_cnt : std_logic := '0';
begin
process(is_ok) -- state switching
begin
if(btn_left = '1' and rising_edge(is_ok)) then
case CurS is
when s0 =>
NxtS <= s0;
when s1 =>
NxtS <= s1;
when s2 =>
NxtS <= s2;
when s3 =>
NxtS <= s3;
when s4 =>
NxtS <= s0;
when s5 =>
NxtS <= s1;
when s6 =>
NxtS <= s2;
when s7 =>
NxtS <= s3;
end case;
end if;
if(btn_right = '1' and rising_edge(is_ok)) then
case CurS is
when s0 =>
NxtS <= s4;
when s1 =>
NxtS <= s5;
when s2 =>
NxtS <= s6;
when s3 =>
NxtS <= s7;
when s4 =>
NxtS <= s4;
when s5 =>
NxtS <= s5;
when s6 =>
NxtS <= s6;
when s7 =>
NxtS <= s7;
end case;
end if;
if(btn_up = '1' and rising_edge(is_ok)) then
case CurS is
when s0 =>
NxtS <= s0;
when s1 =>
NxtS <= s0;
when s2 =>
NxtS <= s1;
when s3 =>
NxtS <= s2;
when s4 =>
NxtS <= s4;
when s5 =>
NxtS <= s4;
when s6 =>
NxtS <= s5;
when s7 =>
NxtS <= s6;
end case;
end if;
if(btn_down = '1' and rising_edge(is_ok)) then
case CurS is
when s0 =>
NxtS <= s1;
when s1 =>
NxtS <= s2;
when s2 =>
NxtS <= s3;
when s3 =>
NxtS <= s3;
when s4 =>
NxtS <= s5;
when s5 =>
NxtS <= s6;
when s6 =>
NxtS <= s7;
when s7 =>
NxtS <= s7;
end case;
end if;
if(btn_center = '1' and rising_edge(is_ok)) then
NxtS <= s0;
end if;
end process;
process(CurS) -- output of state machine
begin
case CurS is
when s0 =>
led <= "10000000";
when s1 =>
led <= "01000000";
when s2 =>
led <= "00100000";
when s3 =>
led <= "00010000";
when s4 =>
led <= "00001000";
when s5 =>
led <= "00000100";
when s6 =>
led <= "00000010";
when s7 =>
led <= "00000001";
end case;
end process;
process(clk_25m) -- debouncing
begin
if(btn_center = '1' or btn_right = '1' or btn_left = '1' or btn_up = '1' or btn_down = '1') then
btn_press <= '1';
else
btn_press <= '0';
end if;
if(rising_edge(btn_press)) then
start_cnt <= '1';
end if;
if(falling_edge(btn_press)) then
start_cnt <= '1';
end if;
if(rising_edge(clk_25m)) then
if(counter /= "10111110101111000010000" and start_cnt = '1') then
counter <= counter + '1';
is_ok <= '0';
elsif(start_cnt = '1' and btn_press = '1') then
is_ok <= '1';
CurS <= NxtS;
start_cnt <= '0';
counter <= "00000000000000000000000";
end if;
end if;
end process;
end behv;
Sometimes the code works as intended but often times there are multiple LED lights turned on or no LED are turned on - I wonder how can this be even possible - and sometimes the state doesn't change when pushing a button (even when holding a button for much longer than 25 ms).
What seems to be the problem. I am running out of ideas.

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