This is my VHDL code in Modelsim. The problem is that output is uninitialized, as you can see in the image. Please tell me what's the problem with my code.
library ieee;
use ieee.std_logic_1164.All;
use IEEE.NUMERIC_STD.ALL;
entity circu_it is
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic );
end circu_it;
architecture Behavioral of circu_it
is
Signal E ,F ,M ,N , L: std_logic;
begin
M <= (A and B and C) after 5ns;
E <= (M or D) after 5ns;
N <= (B nor C) after 5ns;
F <= (N nand A) after 5ns;
L <= not F after 2ns;
Z <= L xor E after 5ns;
end Behavioral;
The testbench of code is the following ......
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity delay_test is
end delay_test;
architecture stimulus of delay_test is
component delay
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Z : out std_logic);
end component;
signal A: std_logic ;
signal B: std_logic ;
signal C: std_logic ;
signal D: std_logic ;
signal Z: std_logic ;
begin
DUT: delay port map ( A => A, B => B, C => C, D => D, Z => Z);
STIMULUS1: process
constant PERIOD: time := 100 ns;
begin
A <= '0';
B <= '0';
C <= '0';
D <= '0';
wait for period;
A <= '0';
B <= '0';
C <= '0';
D <= '1';
wait for period;
A <= '0';
B <= '0';
C <= '1';
D <= '0';
wait for period;
A <= '0';
B <= '0';
C <= '1';
D <= '1';
wait for period;
A <= '0';
B <= '1';
C <= '0';
D <= '0';
wait for period;
A <= '0';
B <= '1';
C <= '0';
D <= '1';
wait for period;
A <= '0';
B <= '1';
C <= '1';
D <= '0';
wait for period;
A <= '0';
B <= '1';
C <= '1';
D <= '1';
wait for period;
A <= '1';
B <= '0';
C <= '0';
D <= '0';
wait for period;
A <= '1';
B <= '0';
C <= '0';
D <= '1';
wait for period;
A <= '1';
B <= '0';
C <= '1';
D <= '0';
wait for period;
A <= '1';
B <= '0';
C <= '1';
D <= '1';
wait for period;
A <= '1';
B <= '1';
C <= '0';
D <= '0';
wait for period;
A <= '1';
B <= '1';
C <= '0';
D <= '1';
wait for period;
A <= '1';
B <= '1';
C <= '1';
D <= '0';
wait for period;
A <= '1';
B <= '1';
C <= '1';
D <= '1';
wait;
end process;
end stimulus;
Your design entity is circu_it. You have instantiated a component called delay. You either need to
write a configuration to bind the two together
change the name of either the component or the entity so that they are the same (so that default binding occurs).
Related
I'm trying to implement a clk Master/Slave JK Flip-flop with two CLK SR Flip-flop components based on NAND Logic in GHDL.
I stumble upon the following error:
several sources for unresolved signal
error during elaboration
I know, as a matter of fact, that the issue is on the Slave latch input SR (S <= Q (Master latch output); R <= nQ (Master latch output)) because of the initial value.
I tried to initialize the values in many ways but didn't manage to pass that error.
I really appreciate any help you can provide.
enter image description here
JK FF Component:
library ieee;
use ieee.std_logic_1164.all;
entity jkff_ms is
port
(
J, K, clk : in std_ulogic;
Q, nQ : inout std_ulogic
);
end entity;
architecture behave of jkff_ms is
component srff
port
(
S, R, clk : in std_ulogic;
Q, nQ : inout std_ulogic -- Q <= (S nand clk) nand nQ; / nQ <= (R nand clk) nand Q;
);
end component;
signal S, R, SRQ, SRnQ : std_ulogic;
signal t0, t1, t2, t3, t4 : std_ulogic;
begin
SRQ <= '1';
SRnQ <= '0';
t0 <= clk nand clk; -- NOT
t1 <= J nand nQ;
t2 <= t1 nand t1; -- NOT
t3 <= K nand Q;
t4 <= t3 nand t3; -- NOT
SR0: srff port map (t2, t4, clk, SRQ, SRnQ);
SR1: srff port map (SRQ, SRnQ, t0, Q, nQ);
end architecture;
JK FF Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity jkff_ms_tb is
end entity;
architecture rtl of jkff_ms_tb is
procedure clk_gen(signal clk0 : out std_ulogic; constant freq : real) is
constant T : time := 1000 ms/freq;
constant ht : time := T/2; -- High_Time
constant lt : time := T - ht; -- Low_Time
begin
assert (ht /= 0 fs) report "clk_plain: High_Time = 0; time resolution to large for freq" severity FAILURE;
loop
clk0 <= '1';
wait for ht;
clk0 <= '0';
wait for lt;
end loop;
end procedure;
component jkff_ms
port
(
J, K, clk : in std_ulogic;
Q, nQ : inout std_ulogic
);
end component;
signal J, K, Q, nQ : std_ulogic;
signal clk_100 : std_ulogic;
begin
clk_gen(clk_100, 100.000e6); -- 100 MHz
assert FALSE report "Time resolution:" & time'image(time'succ(0 fs)) severity NOTE;
JK: jkff_ms port map (J, K, clk_100, Q, nQ);
process
begin
J <= 'X';
K <= 'X';
wait for 10 ns;
J <= '0';
K <= '0';
wait for 10 ns;
J <= '0';
K <= '0';
wait for 10 ns;
J <= '1';
K <= '0';
wait for 10 ns;
J <= '0';
K <= '0';
wait for 10 ns;
J <= '0';
K <= '1';
wait for 10 ns;
J <= '1';
K <= '0';
wait for 10 ns;
J <= '0';
K <= '0';
wait for 10 ns;
J <= '0';
K <= '1';
wait for 10 ns;
assert false report "End of Test";
wait;
end process;
end architecture;
I am trying to show simulation results for a simple And or Invert circuit. I have been struggling to get to the bottom of this for a while now. The code compiles correctly although the simulation does not show the results I expected. The output signal shows as undefined for 5ns then shows a correct signal while the internal signals stated in my design do not show up at all during simulation.
Can anyone check my code for me? Thanks.
Design
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AOI is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
F : out STD_LOGIC);
end AOI;
architecture V1 of AOI is
begin
F <= (A and B) nor (C and D);
end V1;
architecture V3 of AOI is
signal I1, I2, I3 : std_logic;
begin
F <= not I3 after 1 ns;
I3 <= I1 or I2 after 2 ns;
I1 <= A and B after 2 ns;
I2 <= C and D after 2 ns;
end V3;
Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity andorinvertTB is
end;
architecture TB1 of andorinvertTB is
component AOI_component
port(A,B,C,D : in std_logic;
F : out std_logic);
end component;
signal A,B,C,D,F : std_logic;
for G1: AOI_component use entity work.AOI(V3);
begin
stimuli: process
begin
A <= '0'; B <= '0'; C <= '0'; D <= '0'; wait for 10 NS;
A <= '0'; B <= '1'; C <= '0'; D <= '1'; wait for 10 NS;
A <= '1'; B <= '0'; C <= '1'; D <= '0'; wait for 10 NS;
A <= '1'; B <= '1'; C <= '1'; D <= '1'; wait for 10 NS;
wait;
end process;
G1: AOI_component port map ( A=>A, B=>B, C=>C, D=>D, F=>F );
end;
Image of simulation results - Output F undefined at the start and missing internal singals I1, I2 and I3
I'm writing VHDL test bench for full adder
in Simulation i have tried this and getting the correct result
begin
A <= '0';
B <= '0';
C <= '0';
wait for 10 ns;
A <= '0';
B <= '0';
C <= '1';
wait for 10 ns;
A <= '0';
B <= '1';
C <= '0';
wait for 10 ns;
A <= '0';
B <= '1';
C <= '1';
wait for 10 ns;
A <= '1';
B <= '0';
C <= '0';
wait for 10 ns;
A <= '1';
B <= '0';
C <= '1';
wait for 10 ns;
A <= '1';
B <= '1';
C <= '0';
wait for 10 ns;
A <= '1';
B <= '1';
C <= '1';
wait for 10 ns;
wait;
end process;
but i don't want to write all this i just want to use for loop like in verilog
for i in 0 to 7 loop
{A,B,C} <= i;
wait for 10 ns;
end loop;
I Know assigning A, B, C to i is not right in VHDL?
how do we do that what are the correct syntax?
Yes you can - VHDL 2008 allows aggregate assignments.
use ieee.numeric_std_unsigned.all;
for i in 0 to 7 loop
(A,B,C) <= to_slv(i, 3);
wait for 10 ns;
end loop;
This work under VHDL93 with Vivado 2018.1:
loop1: for i in 0 to 7 loop
(a,b,c) <= std_logic_vector(to_unsigned(i,3));
wait for 10ns;
end loop;
You will not need the library use ieee.numeric_std_unsigned.all; (which I do not know)
But you will need the standard ieee library:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Here is the testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity test_tb is
end entity;
architecture Behavioral of test_tb is
signal clk : std_logic;
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
begin
clkpr : process
begin
clk <='1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end process;
test_pr : process
begin
loop: for i in 0 to 7 loop
(a,b,c) <= std_logic_vector(to_unsigned(i,3));
wait for 10ns;
end loop;
wait;
end process;
end Behavioral;
You can try this :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- To use integer and unsigned
...
signal stimuli : std_logic_vector(2 downto 0); -- Equivalent of A, B, C
...
inst_full_adder : full_adder
port map
(
i_a => stimuli(0),
i_b => stimuli(1),
i_carry => stimuli(2),
...
);
...
for i in 0 to 7 loop
stimuli <= std_logic_vector(to_unsigned(i,3)); -- Conversion of your integer in std_logic_vector (3 is the size of your vector)
wait for 10 ns;
end loop;
Right now I am working on a small project in Vivado, a Mealy FSM. The program must detect a 6 bits sequence 001011, and output "1" when the sequence is detected.
The code concerning the sequence detection is doing just fine, but besides that, it must also use Three Flip Flops: JK, D, and T.
Any advice or suggestions on how to add them?
Thank you for your time.
This is the FSM code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence is
port(
clk : in std_logic;
reset : in std_logic;
x: in std_logic;
z : out std_logic;
a : out std_logic;
b : out std_logic;
c : out std_logic;
d : out std_logic;
e : out std_logic;
f : out std_logic);
end sequence;
architecture behavioral of sequence is
type state_type is (Q0, Q1, Q2, Q3, Q4, Q5);
signal state, next_state : state_type;
begin
state_register: process (clk, reset)
begin
if (reset = '1') then --if reset is high, goto state Q0
state <= Q0;
elsif (clk'event and clk = '1') then --if not, and rising
state <= next_state; --edge, go to next state
end if;
end process;
next_state_func: process (x, state)
begin
case state is
when Q0 =>
if x = '0' then
next_state <= Q1;
else
next_state <= Q0;
end if;
when Q1 =>
if x = '0' then
next_state <= Q2;
else
next_state <= Q0;
end if;
when Q2 =>
if x = '1' then
next_state <= Q3;
else
next_state <= Q2;
end if;
when Q3 =>
if x ='0' then
next_state <= Q4;
else
next_state <= Q0;
end if;
when Q4 =>
if x = '1' then
next_state <= Q5;
else
next_state <= Q2;
end if;
when Q5 =>
if x = '1' then
next_state <= Q0;
else
next_state <= Q1;
end if;
end case;
end process;
-- This process controls the output of the sequence detector.
-- Each state has it's own output along with 'z' which indicates
-- the entire sequence 001011 has been detected.
output_func: process (x, state)
begin
case state is
when Q0 => z <= '0';
a <= '1';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q1 => z <= '0';
a <= '0';
b <= '1';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
when Q2 => z <= '0';
a <= '0';
b <= '0';
c <= '1';
d <= '0';
e <= '0';
f <= '0';
when Q3 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '1';
e <= '0';
f <= '0';
when Q4 => z <= '0';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '1';
f <= '0';
when Q5 => z <= '1';
a <= '0';
b <= '0';
c <= '0';
d <= '0';
e <= '0';
f <= '1';
end case;
end process;
end behavioral;
[1]: https://i.stack.imgur.com/pVwxL.jpg - and here is the table that contains the State Diagram Table of the FSM.
Your code is wrong. Take a look at the output_func process; this is combinatorial, and just decodes the current state, without looking at x. The a to f outputs aren't necessary, and are just a 6-bit decode of the current state - why? The z output is set when the current state is Q5, which isn't what you want - the whole process is redundant. You need to set z in your main FSM, when the current state is Q5, and x is 1 - ie. on the next_state <= Q0 transition.
On your actual question - you can't force selection of any particular F/F type with this code - the synthesiser will do whatever it wants, which means that it will implement the whole thing in D types, since JKs have been obsolete for the last 20 years. The same is probably true of T types. You need to start again, and pretend that you have a technology and a library with T, D, and JK. Write these yourself as separate entities, and re-write your code to instantiate these components, instead of allowing the synthesiser to infer them. Re-write your FSM to use JKs - the diagram you gave shows you how. In other words, derive the J and K inputs to each F/F. The z output can be a D-type. You should be able to fit in a T somewhere - I've left that as an exercise for you.
I am trying to simulate my small program and I keep getting error messages and I have not been able to figure out why.
The error messages are:
line 131 error near process
line 132 error near behavioral ; expected type void
The lines:
130 end if;
131 end process;
132 end Behavioral;
I have tried to solve these for hours and I still do not have any clue.
Whole code:
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kuutonen is
Port ( A1 : in STD_LOGIC;
B1 : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC;
E : out STD_LOGIC;
F : out STD_LOGIC;
G : out STD_LOGIC);
end kuutonen;
architecture Behavioral of kuutonen is
signal tmp : std_logic_vector (2 downto 0);
begin
process (clk)
begin
if(tmp = "110")then
tmp <= "000";
end if;
if (A1 = '0' and B1 = '0') then
if (tmp ="000") then
A <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;
if (tmp ="001")then
B <= '1';
A <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;
if (tmp ="010")then
C <= '1';
B <= '0';
A <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;
if (tmp ="011")then
D <= '1';
B <= '0';
C <= '0';
A <= '0';
E <= '0';
F <= '0';
G <= '0';
E <= '1';
if (tmp ="100")then
E <= '1';
B <= '0';
C <= '0';
D <= '0';
A <= '0';
F <= '0';
G <= '0';
tmp <= tmp+1;
end if;
if (tmp ="101")then
F <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
A <= '0';
G <= '0';
tmp <= tmp+1;
end if;
if (tmp ="110")then
G <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
A <= '0';
end if;
end if;
end process;
end Behavioral;
Just from inspection, I'd say it's probably due to a missing "end if;" between the case for tmp=001 and tmp=100.